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260   Chapter Eight

          There has been more success in automating the placement and rout-
        ing of custom-drawn layout cells. Synthesis and cell-based design flows
        allow layout from custom-drawn libraries to be placed and connected by
        automated tools. The library of cells itself must still be drawn by hand,
        but once created the effort of using this layout is greatly reduced. Still,
        the overall density achieved by using these tools is typically less than
        that could be achieved by full custom layout. The time and effort saved
        in layout can come easily at the cost of a larger die area. It seems likely
        that there will always be a strong need for experienced mask designers
        and hand-drawn custom layout.
          Layout is the final design step before chips are manufactured. When
        the layout is complete, it is used to create the photolithography masks,
        and production of prototype chips begins. This date when the layout is
        complete is called tapeout, since in the past the layout of the chip would
        be copied on to magnetic tape to be sent to the fabrication facility. Tapeout
        is one of the most important milestones in any chip design, but it is by no
        means the last. The following chapters will describe the chip manufac-
        turing, packaging, and testing and debugging, which must happen before
        shipping customers.


        Key Concepts and Terms
        Bit pitch                    Power grid
        Contact and via              Physical, temporal, and logical
        Drawn, schematic, and layout  Shielding
        transistor count             Tapeout
        Electromigration             Transistor legging
        Half and full shielding      Well taps
        Layout design rules

        Review Questions

         1. What is the difference between a contact and a via?
         2. What does layout density measure? Why is layout density important?
         3. Why should wide transistors be legged?
         4. What are the uses of drawn transistor count and layout transistor
            count?
         5. What is the difference between device-limited and wire-limited layout?
         6. What is the difference between physical, logical, and temporal
            shielding?
         7. [Bonus] Use colored pens or pencils to draw the layout for a two-input
            NOR gate. Use a different color for each different material.
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