Page 210 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 1: INTEGER-N FREQUENCY
SYNTHESIZERS Ronald E. Best 128
To illustrate the theory of frequency synthesizers we now will design an actual system that
uses the design procedure described in Chap. 5 and shown in the flowchart in Fig. 5.1.

Case Study: Designing an Integer-N PLL Frequency Synthesizer

The frequency synthesizer is required to produce a set of frequencies in the range from 1 to 2
MHz with a channel spacing of 10 kHz—meaning frequencies of 1000, 1010, 1020, and so on
up to 2000 kHz will be generated. For this design, we use the popular 74HC/HCT4076 CMOS
device which is based on the old industry standard CD 4046 originally introduced by RCA.
This circuit contains three different phase detectors, an EXOR gate, a JK-flipflop, and a PFD
(with voltage output). Because noise must not be considered in this design, we use the PFD as
phase detector. Because this detector offers infinite pull-in range for any type of loop filter, we
use the simplest of these, the passive lead-lag. The supply voltage U is chosen as 5 V. With
B
these assumptions, we are ready to start the design, following the procedure shown in Fig. 5.1
(Chap. 5).

Step 1. Determine ranges of input and output frequencies. The input frequency is constant,
f = 10 kHz. The output frequency is in the range of 1 to 2 MHz; thus, f 2min = 1 MHz, f 2max =
1
2 MHz.
Step 2. The divider ratio must be variable in the range N = 100 to 200. The PLL will be
optimized (ζ = 0.7) for the divider ratio , as will be shown in
step 3.

Step 3. Determination of damping factor ζ. Selecting ζ = 0.7 at N = N mean yields the
following minimum and maximum values for ζ:

This range is acceptable.
Step 4. Noise is not of concern in this PLL design, so the procedure continues with step 12.

Step 12. Selection of the phase detector type. The PFD (with voltage output) is chosen, as
noted in the introductory remarks. The phase detector gain becomes K = 5/4π = 0.4 V/rad.
d
Step 13. VCO layout. According to the data sheet of the 74HC4046A IC, the VCO operates
linearly in the voltage range of u = 1.1 to 3.9 V approximately. Therefore, the characteristic of
f
Fig. 6.9 can be plotted. If the VCO input voltage exceeds about 3.9 V, the VCO generates a
very high frequency (around 30 MHz); if it falls below 1.1 V, the VCO frequency is extremely
low—in other words, only

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