Page 215 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 1: INTEGER-N FREQUENCY
SYNTHESIZERS Ronald E. Best 131
Only the PC2 OUT is used in this application. For the down scaler, an eight-bit presettable
down counter of type 74HC40102 or 74HC40103 is used. The 74HC40102 consists of two
cascaded BDC counters, whereas the 74HC40103 is a binary counter. When the PE (preset
enable) input is pulled “low,” the data on input port P0 through P7 are loaded into the
counter. The counter counts down on every positive transition at the CP input (count pulse). If
the counter has counted down to 0, the TC output (terminal count) goes low. Connecting TC
with PE forces the counter to reload the data on the next counting pulse. If N is the number
represented by the data bus, the counter divides by N + 1 (and not by N). To scale down by a
factor of 100, for example, we must therefore apply N = 99 to the input port.
As mentioned earlier, the Philips company provides a diskette with a design program for
52
this type of PLL IC. (This program can also be downloaded from www.nxp.com, a website
maintained by the Philips company.) The author repeated the design using this program and
got design parameters very similar to those obtained by his own procedure.

Single-Loop and Multi-Loop Frequency Synthesizers

In Secs. 6.2 and 6.3, we exclusively considered frequency synthesizers which were built from
one single loop. Such synthesizers were capable of creating a set of frequencies that were an
integer multiple of a given reference frequency. We will see in this section that single-loop
synthesizers can become impractical when it comes to generating a large range of frequencies
with a very small channel spacing.
Think, for example, of a synthesizer which would be required to generate frequencies in the
range of 100 to 200 MHz with a channel spacing of 1 kHz. Of course, we could implement a
synthesizer as shown in Fig. 3.1, having a reference frequency of 1 kHz and using a divide-by-
N counter having a scaling factor N in the range of 100,000 to 200,000. Such a system would
show up two flaws: first of all, it would be slow because it needs about 10 to 20 reference
cycles to switch from one channel to another—that is, it would settle in perhaps 20 ms.
Second, it would probably have poor noise performance. As will be shown in Sec. 6.7, the
phase jitter at the output of the VCO increases with the square of the scaling factor N.
Another idea would be to use two separate synthesizers, a “course” synthesizer creating
the frequency range from 100 to 200 MHz in steps of 1 MHz, and a “fine” synthesizer
generating frequencies in the range of 0 to 1 MHz in steps of 1 kHz. (We will see later that the
“fine” synthesizer must not necessarily be slow.) To add coarse and fine frequencies, we
would use a mixer (cf. Fig. 6.11).
An extremely simple numerical example will demonstrate, however, that this simple
arrangement would not work as expected. Assume, for example, that the coarse frequency f is
1
100 MHz and the fine frequency f is 1 kHz. An ideal mixer would multiply both input
2
signals; hence, at its output we would have an upper

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