Page 255 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 1: INTEGER-N FREQUENCY
SYNTHESIZERS Ronald E. Best 151
of the VCO. As we will see, this can lead to spurious sidebands in the VCO output signal,
which affects its spectral purity, of course. The effects of the ripple are different for the
various types of phase detectors and must therefore be treated separately.
Let us look first at what can happen when the EXOR phase detector is used. In a PLL
frequency synthesizer (Fig. 3.1) with divider ratio N = 1, the instantaneous phase of the VCO
output signal would be modulated by a signal whose frequency is twice that frequency.
Obviously, this cannot have an impact on the VCO frequency. When N = 2, nothing happens
again, because now the instantaneous phase of the VCO output signal is modulated by a signal
whose frequency is identical with the VCO frequency. But adverse effects start as soon as N
becomes 3 or larger. For general N, the frequency of the VCO output signal is N · f , and
ref
the ripple signal has a fundamental frequency of 2f ref. For N = 3, spurious sidebands appear at
the VCO output whose frequencies are N · f ± 2f , N · f ± 4 · f , and so on. If
ref ref ref ref
the multiplier phase detector is used instead of the EXOR, spurs will be created at the same
frequencies.
The situation is similar when the JK-flipflop is used as a phase detector. In the locked state,
the JK-flipflop generates an output signal whose frequency is identical with the reference
frequency (see Fig. 2.9). If the divider ratio of the frequency synthesizer is 1, the ripple on the
VCO input signal only alters the duty cycle of the VCO output signal but does not generate
spurious sidebands. Spurious signals appear, however, when N becomes 2 and greater. Then
the spectrum of the output signal contains lines at frequencies N · f ref ± f , N · f ref ±
ref
2f , and so on.
ref
When the PFD with voltage output is used as a phase detector, spurious side-bands at a
subharmonic of the reference frequency can show up, which is very disturbing because there is
a good change for those spurs to lie inside the loop bandwidth B . These spurs are created by a
L
phenomenon called backlash, which will be described in the following. When the PLL
operates exactly on its center frequency, the output signal of the PFD is theoretically in the 0
state all the time. The reference signal u and the (scaled-down) output signal u ′ (refer to
1 2
Fig. 6.21a) would then be exactly in phase. In reality, the frequency of the VCO output signal
will slowly drift away, which causes a time lag between these two signals. When this time lag
is 10 ps, for example, the PFD will theoretically generate a correction pulse whose duration is
10 ps as well. Because the logical circuits inside the PFD have nonzero propagation delays and
rise times, the PFD is never capable of generating such short pulses. It will produce a
correction pulse only when the delay between the u and u ′ signals has become greater than
1 2
a time interval called backlash. For high-speed CMOS circuits, the backlash is typically in the
range of 2 to 3 ns. The PFD never generates an output pulse shorter than the backlash interval.
Fig. 6.21b shows the PFD output signal u , which has been generated just at the instant where
d
the positive edge of the u signal led the positive edge of u ′ by an amount equal to the
2
1
backlash, denoted as τ here. The width of the correction pulse is nearly equal to τ in this
1 1
case. Unfortunately, each real device contains parasitic capacitances. In our example, parasitic

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