Page 280 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 2: FRACTIONAL-N FREQUENCY
SYNTHESIZERS Ronald E. Best 166
part of the divider ratio, while F is the fractional part. Fraction F is stored in a register and is
in the range of 0 to 1. The SDM creates a binary output signal in every reference cycle. If a
logical 1 output signal is assigned the numerical value 1, and the logical 0 a numerical value of
0, then the numerical output signal becomes F on average. When F is 0.37, for example, the
SDM output is 1 in 37 of 100 reference cycles on average. The output signal of the SDM is
used to switch the divider ratio N of the programmable ÷N counter from N to N + 1. Usually,
the ÷N counter is either a dual-modulus or a four-modulus counter, as discussed in Secs.
6.3.2 and 6.3.3. In the example shown, the output of the SDM is binary. Other cases exist,
however, where the SDM outputs other types of digital signals—for example, ternary,
quaternary, or in the most general case, m-ary. When the SDM output signal is m-ary, the
divider ratio is not only switched between N and N + 1, but between m different values—for
example, N − 3, N − 2 thru N + 2, N + 3, N + 4.
The theory of sigma-delta modulators is quite complex, so we will discuss it in Sec. 7.4.3 in
greater detail. Because SDMs have become popular originally in A/D and D/A converters, we
will review those applications first before entering into details on SDMs in frequency
synthesizers.

Reviewing the ΣΔ Modulator

When designing a ΣΔ modulator to be applied in a fractional-N frequency synthesizer, we will
encounter a number of particular problems such as loop stability, quantization noise,
oversampling, and the like. To get familiar with these specific topics, we will discuss them in
more detail using the example of the ΣΔ ADC.

The ΣΔ A/D converter
In the ΣΔ ADC, oversampling is used to enhance the resolution (number of bits) of a low-
resolution A/D converter. It then becomes possible to increase the resolution of an extremely
simple one-bit ADC to 16 bits, for example, or even more. Several types of ADCs make use of
oversampling; the ΣΔ is just one possible configuration. We shall first explain the
oversampling principle at an ADC configuration that is simpler than the ΣΔ converter. The ΣΔ
ADC will be discussed thereafter.
Let’s start with a one-bit ADC, as shown in Fig. 7.5a. The analog input signal U is
A
sampled at frequency f and applied to the ADC. The transfer characteristic of the one-bit
F
ADC is plotted in Fig. 7.5b. The analog signal U is supposed to be in the range of 0 to 1,
A
which can be represented by a voltage range from 0 to 1 V or any other range. The ADC is
nothing more than a quantizer. Its output signal U is a quantized version of the input signal
Q
as sketched by the solid curve. The switching threshold of this quantizer is at U = 0.5. Input
A
signals less than 0.5 are quantized as 0, and input signals larger than 0.5 as 1. The quantization
step—the difference between the two logical levels of the quantizer—is Q = 1 in this example.

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