Page 40 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL BUILDING BLOCKS Ronald E. Best 28
transition of u then sets the UP flipflop. When u ′ goes high thereafter, the DN flipflop will
1 2
also be set, thus both flipflops are momentarily in the 1 state. This forces the output of the
AND gate into the 1 state, and both flipflops will be reset. Now suppose there is a delay t d
between the output of the AND gate and the clear (C ) inputs of the flipflops. If this delay is
D
chosen 15 ns, for example, both flipflops will remain ON simultaneously for 15 ns upon the
positive transition of u ′. Because both current sources carry the same current, the net
2
current flowing into the load during this interval is zero. But what is the reason to have both
flipflops set at the same time? To answer this question, assume that the phase error is
extremely small so the time delay between the positive transitions of u and u ′ is very
1 2
short—for example, only 5 ps. Let us call that time delay t . When the positive transition in u 1
e
occurs at time t , the UP flipflop is set to the 1 state at t . The DN flipflop is set then to the 1
0 0
state at t + t . Because the reset signal is delayed by t , both flipflops are reset at t + t + t .
d
e
0
e
d
0
Consequently, the UP flipflop is set during a time interval t + t , and the DN flipflop is set
e d
during a time interval t . The net charge flowing into the load depends on t alone, of course,
e
d
because both currents flowing when both flipflops are set cancel. For the values chosen earlier
(t = 5 ps, t = 15 ns), the UP flipflop will be ON for 15.005 ns, but the DN flipflop is ON
e d
during only 15.000 ns. Hence, the net charge flowing into the load is the peak current
multiplied by a mere 5 ps. We recognize that the current output PFD is able to react properly
onto even the smallest phase error—in other words, to inject arbitrarily small amounts of
charge into the load.
Let us see now how the voltage output PFD (cf. Fig. 2.11) performs under the same
conditions. The positive transition of u first sets the UP flipflop. The output signal of the
1
flipflop will not instantaneously swing to the positive supply voltage U but will start rising
B
after some propagation delay t and approach the final level with a finite slope given by rise
P
time t . After t seconds, the positive transition of u ′ occurs, which causes the output signal
R e 2
of the DN flipflop to go positive as well after the propagation delay t . When both flipflop
P
outputs have reached a level that is sufficient to switch the AND gate to the 1 state, both
flipflops start to get reset, and the output signal of both flipflops returns toward ground. When
the delay t is shorter than the sum of propagation delay t and rise time t neither the P-
R
P
e
channel nor the N-channel MOS transistor can turn ON, and the output of the PFD remains in
the high impedance state all the time. In other words, the PFD is unable to react to small phase
errors. Only when the delay t becomes larger than the sum of propagation delay and rise time
e
of the D flipflop (followed by a MOS transistor) will the PFD output become active. For
standard CMOS circuits, the minimum t value is in the order of some nanoseconds. This
e
phenomenon is called backlash, and it leads to undesired sidebands in the spectrum of the
VCO output signal. These sidebands are commonly referred to as spurious frequencies, spurs,
or tones. We will deal with these spurs in greater detail in Sec. 6.7.3.

Loop Filters (First Order)

As we have seen in Sec. 2.4, the output signal u (t) of the phase detector consists of a number
d