Page 75 - Phase-Locked Loops Design, Simulation, and Applications
P. 75

MIXED-SIGNAL PLL ANALYSIS   Ronald E. Best                                              53
               more difficult to obtain a stable higher-order system than a lower-order one. We will deal with
               higher-order loops in Chap. 9.


               A special case: the first-order PLL

               The first-order PLL is an extremely simple system. When we omit the loop filter, F(s) in Eq.
               (3.7) becomes 1, and for the phase-transfer function we obtain



                                                                                           (3.41)




               This is the transfer function  of a first-order low-pass filter having a 3-dB angular corner
               frequency ω     = K K /N. As we will see in Sec. 3.9.1, the term K K /N is identical with the
                           3db    0 d                                           0 d
               hold range of the PLL.
                 Because the hold range is generally much larger than the natural frequency ω  of second-
                                                                                              n
               order PLLs, the first-order PLL has large bandwidth and hence tracks phase and frequency
               variations of the input signal very rapidly. Due to its high bandwidth, however, the first-order
               PLL does not suppress noise superimposed to the input signal. Because this is an undesirable
               property in most PLL applications, the first-order PLL is rarely utilized here. First-order PLLs
               really do exist in applications where noise is not a primary concern. In Chap. 11, we will deal
               with a first-order all-digital PLL system frequently used in FSK modems.



               PLL Performance in the Unlocked State

               As we have seen in Sec. 3.2, the linear model of the PLL is valid only when the PLL is in the
               locked state. When the PLL is out of lock, its model becomes much more complicated and is
               nonlinear, of course. In this section, we shall develop a mathematical model that is valid in the
               unlocked state of the PLL. Based on that model, we will develop a mechanical analogy that is
               much simpler to analyze and that will help us derive the relevant parameters describing the
               acquisition and lock-out processes of PLLs.
                 This analogy should answer the following questions:

               ■ Under what conditions will the PLL get locked?
               ■ How much time does the lock-in process need?
               ■ Under what conditions will the PLL lose lock?



               Mathematical Model for the Unlocked State

               The following discussion assumes that a phase detector with voltage output is used. The
               results are valid, however, also for charge  pump PDs, but in the equations some minor
               modifications would have to be made (for example, setting K  instead of K , and so on).
                                                                          P            d



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