Page 89 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 62
quantitative relationships among these four parameters are plotted in Fig. 3.9 for most
practical cases. We can state in advance that the hold range Δω H is greater than the three
remaining parameters. Furthermore, we know that the pull-in range Δω must be greater than
P
the lock range Δω . The pull-in range Δω is greater than the pull-out range Δω in most
L P PO
practical designs, so we get the simple inequality

In many texts, the term capture range can also be found. In most cases, capture range is an
alternative expression for lock range; sometimes, it is also used to mean pull-in range. The
differentiation between lock-in and pull-in ranges is not clearly established in some books, but
we will maintain it throughout this text. 1

Key Parameters of the PLL

In Sec. 3.8, it was demonstrated that the dynamic performance of the PLL is governed by a set
of key parameters:

■ The lock range Δω
L
■ The pull-out range Δω
PO
■ The pull-in range Δω
P
■ The hold range Δω
H
Here, we will define parameters relating to the time required for the PLL to get locked:

■ The lock time T . The time the PLL needs to get locked when the acquisition process is a
L
(fast) lock-in process
■ The pull-in time T . This is the time the PLL needs to get locked when the acquisition
P
process is a (slow) pull-in process
To design a PLL system, we need equations that tell us how these key parameters depend
on the parameters of the circuit—that is, the time constants τ and τ of the loop filter, the gain
2
1
factors K or K , K , and K (when the active lead-lag filter is used), and the divider ratio N of
d P 0 a
an optional down scaler. In the following, we will derive a number of approximate design
equations for these parameters. Unfortunately, these equations depend on the type of phase
detectors and loop filters used. To make the design easier, the results will be shown in tables.
Moreover, we will demonstrate in Chap. 10 that the design can be performed by a dedicated
computer program developed by the author.

Hold range Δω H

First of all, let us state that the hold range is a parameter of more academic interest. The hold
range is the frequency range in which a PLL is able to maintain

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