Page 93 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 64
At the limit of the hold range, θ = π/2 and sin θ = 1. Therefore, we obtain for the hold
e e
range the expression

The DC gain F(0) of the loop filter depends on the filter type. For the passive lead-lag filter,
the DC gain F(0) = 1. For the active lag filter, the DC gain is F(0) = K . For the active PI
a
filter, F(0) = ∞, at least theoretically. When phase detector type 1 is used, we get for the hold
range

(3.52)

When the active PI filter is used, the actual hold range is limited by the frequency range
covered by the VCO.
Phase detector type 2. When the EXOR phase detector is chosen, the maximum phase
error in the steady state can be π/2. In contrast to phase detector type 1, the equation
is valid for all values of θ in the range −π/2 < θ < π/2. Hence, we get from Eq.
e e
(3.51)

(3.53)

Note again that F(0)—the loop filter gain at DC—depends on the type of loop filter chosen,
as described earlier.

Phase detector type 3. When the JK-flipflop phase detector is chosen, the average phase
detector output is proportional to the phase error θ over the whole range −π < θ < π. By
e
e
an analogous argumentation, we get for the hold range

(3.54)

Phase detector type 4a. When the PFD with voltage output is used, the average phase
detector output is proportional to the phase error over the range −2π < θ < 2π. Hence, we
e
get for the hold range

(3.55)

To get the hold range for the three different types of loop filters, we have to insert the
correct DC gain into F(0) in Eq. (3.55). For the previously discussed types of phase detector,