Page 94 - Phase-Locked Loops Design, Simulation, and Applications

we put F(0) = 1 for the passive lead-lag filter, F(0) = K for the active lead-lag filter, and F
a
(0) = ∞ for the active PI filter. As we shall now see, we will have to set F(0) = ∞ for all filter
types. What is the reason for this?
Let us consider a cascade connection of a voltage output PFD (cf. Fig. 2.11) and a passive
lead-lag filter (cf. Fig. 2.17a). When the PFD output floats, the

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