Page 91 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 63
lock statically. As we have seen in Sec. 3.8, the PLL locks out forever when the frequency of
the input signal exceeds the hold range, so most practitioners don’t even worry about the
actual value of this parameter.
The magnitude of the hold range is obtained by calculating that frequency where the phase
error is at its maximum. As we have seen in Sec. 2.4, this maximum value depends on the type
of phase detector used. With a multiplier phase detector, the PLL can maintain lock at a phase
error slightly less than 90°. The same holds true for the EXOR phase detector. When the JK-
flipflop phase detector is used, however, the PLL can stay locked up to a phase error of 180°,
and for the PFD this value is even 360°. The equation for the hold range Δω will therefore
H
be different for each type of phase detector. Let us first analyze the hold range for the
multiplier phase detector.
Phase detector type 1. To get the hold range Δω , we must determine the frequency for
H
which the steady state phase error becomes 90°. At the limit of the hold range, the input
frequency ω is given by
1

For the phase signal θ (t), we therefore get
1

The Laplace transform of the phase signal then becomes

The phase error can now be calculated according to Eq. (3.27)

Using the final-value theorem of the Laplace transform, we calculate the final phase error θ e
(∞) in the time domain

(3.51)

Remember that the PLL network was linearized when the Laplace transform was
introduced. Consequently, Eq. (3.51) is valid for small values of θ only. For greater values of
e
phase error, we would have to write