Page 255 - Power Electronics Handbook

Parallel-capacitor commutation 245

(ii) What are the limits on the minimum and maximum duration of the
output pulse? Once again, the wider the limits, the more flexible the
system and therefore the higher its performance.
(iii) Is the commutation capacitor voltage inherently increased in
proportion to the load current to be commutated? Such an increase is
usually desirable since the capacitor can be optimised to operate over
a wide range of loads, the voltage on the capacitor and therefore the
commutation energy which it stores, increasing with load current,
when it is most required.
(iv) If commutation were to be unsuccessful on the first attempt, say due
to an overload, would it be attempted once more and be successful
when the load reduced? Such a feature is highly desirable and is
superior to systems where once a commutation is attempted and fails,
the commutation mechanism is locked and cannot take part in any
further operations, causing a once-for-all failure of the system.
(v) Is the current rating of the main thyristor increased by the
commutation process? For high-frequency applications a consider-
able amount of energy is expended in the series of commutations, and
if this were all to flow through the main power semiconductor its
rating would be increased appreciably, so that commutation systems
which avoid this are obviously superior.
(vi) The sixth parameter is of importance when considering chopper or
inverter circuits and is related to the inverter or chopper
configuration more than to the commutation method. This is whether
there is a low-impedance fault current path across the supply, since if
such a path does exist then a commutation failure would cause the
current to rise rapidly, destroying the semiconductor devices.
In the detailed description of the four commutation methods, given in
the following sections, chopper circuits will be used as illustrations, since
they are much simpler than inverter circuits and allow attention to be
placed on the commutation technique. The same principles apply for
inverters and these are described in Chapter 13.

11.3 Parallellcapacitor commutation

The parallel-capacitor commutation method was shown in Figure 11.2(a).
To explain its operation, assume that capacitor C is charged to a voltage
V,, from an earlier cycle, with the polarity indicated. The load current just
prior to switch S, closing is ZW) and is assumed to remain constant during
the short discharge period of capacitor C. If the reverse recovery current
through thyristor THI is also neglected, then the time during which the
thyristor is reverse biased (t,) after the switch is closed is given by equation
(1 1.1) and for commutation to be successful this time must exceed the turn-
off time of the thyristor.

(11.1)

The rate of re-application of forward voltage across the thyristor is
determined by the commutation capacitor discharging through the load