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Geng(SMH)_CH19.qxd 04/04/2005 20:00 Page 19.5

INSPECTION, MEASUREMENT, AND TEST

INSPECTION, MEASUREMENT, AND TEST 19.5

the very real distinction between these because, though defects are the reality, circuit model-based
electronic design automation (EDA) tools can only deal with faults, and good fault coverage can still
result in poor defect coverage. The stuck-at fault is the most widely used fault model in digital
designs because it is the easiest to use but often not the most relevant. Other digital fault models are
used as well—bridging, transition time, and path delay.
The “stuck-at fault” term means a node or logic gate is stuck at either a “0” or “1” level. This
stuck-at condition must now be propagated to the output of the device for observation. If it can be
observed it is called a detected fault. The goal is to cover the stuck-at detectable faults to 95 percent
or higher. This in combination with other forms of tests that will be explored later, will provide cov-
erage close to 100 percent.
There are many reasons that a fault may not be detectable. Untestable faults are faults that will
not propagate to the device’s output because of the device’s design. Undetected faults are those that
cannot be detected in a reasonable amount of time, usually due to a massive fan in or fan out in the
circuit design. The untested fault is one that the fault analysis tool did not evaluate. Understanding
and using all these IC fault types along with a high-performance analysis tool, IC manufacturers can
design and build high-quality circuits. There are also other indirect methods of testing, such as I ,
DDQ
which can catch these kinds of errors without direct logic analysis. I will be described more in
DDQ
the section “Functional, Structural, and Defect-Based Tests.”
The fault coverage model relies on testing to realize its potential to catch these physical imper-
fections. Other error types that can be detected by testing are design errors or package errors. Design
errors can result from the merging of designs from different people or tools. Package errors may
occur in assembling the die into the package or connections to the IC pins.
There is also a trend to package multiple die in one package, usually to save cost. There is a
process called known-good die (KGD) in which all the die are fully tested to the level that would nor-
mally be done at the final test before assembly, saving the cost of scrapping, packaging, and other
potentially good die in the event of a bad die being assembled in the multichip package.

19.1.3 The Importance of Tests Throughout the Product Lifecycle

In today’s semiconductor market, product lifecycles are shrinking as new products are introduced
and obsoleted at an unprecedented rate. The product lifecycle can be characterized by three major
phases, each with its own challenges and goals—time-to-market, time-to-volume, and time-to-profit
as seen in Fig. 19.2. Throughout the lifecycle and in each phase, testing plays a key role by ensur-
ing the performance, functionality, and quality of the devices.
Time-to-Market. To be successful, a product must meet its market window, which is open for only
a limited time. A delay in market entry means the product will have a shorter lifetime, resulting in a
loss of revenue or even complete loss of business to competitors who already have products in the
market. From a test perspective, this means the test plan for a new device must be developed as
quickly as possible, yet still must meet the fundamental goal of characterizing the device’s perfor-
mance and verifying its functionality.

Time-to-Volume. After rushing the device to market, the next step is to ramp up production, bring-
ing the device into high-volume manufacturing. During this phase, the manufacturing process is
automated and refined to meet the volume expectations of the market. The test results in manufac-
turing must correlate to the testing done during the design validation and device characterization
stages. It is also important for test results to be repeatable over time and across different test cells.
*
The Automated Test Cell. SEMI standards provide a helpful framework for defining the need for
an automated test cell as opposed to simply a stand-alone automated test system. SEMI Standard
E40-0703 defines a process agent as “an intelligent system within a factory which is independently

* SEMI, http://www.semi.org/.

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