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Geng(SMH)_CH19.qxd 04/04/2005 20:00 Page 19.7

INSPECTION, MEASUREMENT, AND TEST

INSPECTION, MEASUREMENT, AND TEST 19.7

First, the raw stimulus and measurement performance of two or more test systems need to be com-
parable. In this case a stimulus/measurement standard is run on each system and the raw perfor-
mance of the systems is compared. The second component of correlation is the device performance.
The measured performance of the actual device should have a consistent result on two or more plat-
forms. Variations in either of these measures identify if the system or the device is drifting or is
erratic with respect to the last sample.

Time-to-Profit. As the device continues to ship in volume and approaches maturity and obsoles-
cence, profitability is the key concern. The goal during this phase of the product lifecycle is to min-
imize manufacturing costs, including test costs, while maintaining reliable quality and product
delivery to customers.
Defining Cost-of-Test (COT). Since COT can make up 3 to 10 percent of the total cost of manu-
facturing, driving down COT is key to reducing manufacturing costs and ultimately to growing prof-
itability. A simple definition of COT is the “test cost per good part.” To determine this metric, the
yearly test costs associated with a test cell are divided by the number of good devices processed by
the test cell during the year. The major cost factors include acquisition costs, cost of the test equip-
ment, floor space, and yearly recurring costs such as labor, utilities, maintenance, support contracts,
spare parts, and consumables. The number of good devices per year will depend on the test yield,
*
throughput of the test cell and utilization of the test cell. SEMI Standard E35 provides a compre-
hensive look at the costs associated with testing.
†
Overall Equipment Efficiency (OEE). SEMI Standard E58 provides a good basis for under-
standing the OEE metric and defines the availability and utilization that are important components
of OEE. Availability is a straightforward measure of the percentage of the total manufacturing time,
typically some part of a 168-h week, that a test system is able to perform its intended function. A num-
ber less than 168 h is used since in a typical manufacturing operation, the system is assumed to be
unavailable for maintenance and other nonproduction use for some portion of the week. Utilization
takes availability a step further; it is a measure of the percentage of the total manufacturing time that
the system actually performs its intended function. Finally, OEE takes another step forward and mea-
sures how efficiently the system is performing when it is being utilized. For example, if a test sys-
tem is scheduled for 150 of 168 h in a week, and is actually available for 100 h, its availability
is 100/150 = 67 percent. If it is actually used to test devices for 75 h, the system is 75/150 = 50
percent utilized. If the test system is expected to produce 10,000 good parts while it is utilized, but
due to system problems can only produce 8000 good parts, then the system OEE is 50 percent ×
8000/10,000 = 40 percent. From this analysis it can been seen that OEE actually accounts for device
yield performance by looking at the expected good parts produced and not the total parts tested.

19.1.4 Business Models
In the past, semiconductor manufacturers or integrated device manufacturers (IDMs) used a business
model where they owned and controlled all the processes and equipment in the vertical market segment
required to design, develop, produce, test, package, and ship devices to their customers. This model
requires a large amount of capital and human resources and tends to favor large, well-established
companies.
A new model has emerged, for a number of reasons, which segments all these different opera-
tions among many companies. This model is called the subcontract manufacturing (SCM) model.
In this new model, there are two main subdivisions—the design house that implements the IC design
part and the foundry that does the fabrication, packaging, and testing of the silicon. This model has
a significant shift in expenses, the design house having a significantly lower capital outlay expense than
the foundry. This lower capital expenditure model also fueled a number of startup IC design houses.

* SEMI E35-0701, Cost of Ownership.
† SEMI E58-0703, Automated Reliability.

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