Page 137 - Six Sigma for electronics design and manufacturing

Six Sigma for Electronics Design and Manufacturing
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Figure 4.1 First-time yield (FTY) IC wire bonding example.

nential power expansion [Equation (4.8)], or by independently calcu-
lating the total defects in 100 ICs.

1. Process defects per wire bond = 100 PPM/1,000,000 = 0.0001
Total wire bond opportunities/IC = 512 bonds
DPU /IC = 512 · 0.0001 = 0.0512
FTY = e – DPU = e –0.0512 = 0.95 or 95% FTY using the Poisson dis-
tribution
1
n
2. Y T = Y A = (1 – DPU) = (1 – 0.0512) = 0.9488 or 94.88% using
power expansion
3. FTY actual for 100 ICs = 51,200 bonds @ 0.0001 = 5.12 defects per
100 ICs or 94.88% FTY
It can be seen that the FTY actual, which is the most accurate, is
closely approximated by the Poisson distribution, and is exactly equal
to the power expansion. These differences are small at the 100 PPM
level, which is approximately four sigma quality. In the case of poor
quality, such as those below two sigma, the differences in the calculat-
ed yield among the three methods become large. In that case, using
the actual calculations is the most prudent way to obtain the yield.
Note that the resultant five defects do not necessarily imply that five
ICs are defective; one IC could have more than one defect.

4.2.2 Determining assembly yield and PCB and
product test levels in electronic products
In typical electronic manufacturing lines, printed circuit boards
(PCBs) are assembled and tested individually. Multiple PCBs are then
assembled into finished products, which are tested. The test engineers