Page 1134 - The Mechatronics Handbook

address indexes that are translated through the TLB, potentially reducing the overall delay. With larger
page sizes, virtual caches do not have advantage over physical caches in terms of access time.

Input/Output Subsystem
The Input/Output (I/O) subsystem transfers data between the internal components (CPU and main
memory) and the external devices (disks, terminals, printers, keyboards, scanners).

Peripheral Controllers
The CPU usually controls the I/O subsystem by reading from and writing into the I/O (control) registers.
There are two popular approaches for allowing the CPU to access these I/O registers—I/O instructions
and memory-mapped I/O. In an I/O instruction approach, special instructions are added to the instruc-
tion set to access I/O status flags, control registers, and data buffer registers. In a memory-mapped I/O
approach, the control registers, the status flags, and the data buffer registers are mapped as physical
memory locations. Due to the increasing availability of chip area and pins, microprocessors are increasingly
including peripheral controllers on-chip. This trend is especially clear for embedded microprocessors.
Direct Memory Access Controller
A DMA controller is a peripheral controller that can directly drive the address lines of the system bus.
The data is directly moved from the data buffer to the main memory, rather than from data buffer to a
CPU register, then from CPU register to main memory.

System Interconnection
System interconnection is the facilities that allow the components within a computer system to commu-
nicate with each other. There are numerous logical organizations of these system interconnect facilities.
Dedicated links or point-to-point connections enable dedicated communication between compo-
nents. There are different system interconnection configurations based on the connectivity of the system
components. A complete connection configuration, requiring N(N – 1)/2 links, is created when there is
one link between every possible pair of components. A hypercube configuration assigns a unique n-tuple
{1, 0} as the coordinate of each component and constructs a link between components whose coordinates
differ only in one dimension, requiring N log N links. A mesh connection arranges the system components
into an N-dimensional array and has connections between immediate neighbors, requiring 2N links.
Switching networks are a group of switches that determine the existence of communication links
among components. A cross-bar network is considered the most general form of switching network and
uses an N ¥ M two-dimensional array of switches to provide an arbitrary connection between N
components on one side to M components on another side using NM switches and N + M links. Another
switching network is the multistage network, which employs multiple stages of shuffle networks to provide
a permutation connection pattern between N components on each side by using N log N switches and
N log N links.
Shared buses are single links which connect all components to all other components and are the most
popular connection structure. The sharing of buses among the components of a system requires several
aspects of bus control. First, there is a distinction between bus masters, the units controlling bus transfers
(CPU, DMA, IOP) and bus slaves, the other units (memory, programmed I/O interface).
Bus interfacing and bus addressing are the means to connect and disconnect units on the bus. Bus
arbitration is the process of granting the bus resource to one of the requesters. Arbitration typically uses
a selection scheme similar to interrupts; however, there are more fixed methods of establishing selection.
Fixed-priority arbitration gives every requester a fixed priority, and round-robin ensures every requester
the most favorable at one point in time. Bus timing refers to the method of communication among the
system units and can be classified as either synchronous or asynchronous. Synchronous bus timing uses
a shared clock that defines the time other bus signals change and stabilize. Clock sharing by all units
allows the bus to be monitored at agreed time intervals and action taken accordingly. However, the
synchronous system bus must operate at the speed of the slowest component. Asynchronous bus timing

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