Page 1136 - The Mechatronics Handbook

determine instruction lengths and steer the instructions to the second stage, where the actual instruction
decoding is performed. The second alternative, in Fig. 42.10(b), involves predecoding and marking instruc-
tion lengths in the instruction cache. This design methodology has been effectively used in decoding X86
5
variable instructions. The primary advantage of this scheme is the simplification of the number of decode
stages in the pipeline design. However, the method requires a larger instruction cache structure for holding
the resolved instruction information.
Architecture Model
Several instruction set architecture models have existed over the last three decades of computing. First,
CISC (complex instruction set computers) characterized designs with variable instruction formats,
numerous memory addressing modes, and large numbers of instruction types. The original CISC phi-
losophy was to create instructions sets that resembled high-level programming languages in an effort to
simplify compiler technology. In addition, the design constraint of small memory capacity also led to
the development of CISC. The two primary architecture examples of the CISC model are the Digital
VAX and Intel X86 architecture families.
RISC (reduced instruction set computers) gained favor with the philosophy of uniform instruction
lengths, load-store instruction sets, limited addressing modes, and reduced number of operation types.
RISC concepts allow the microarchitecture design of machines to be more easily pipelined, reducing the
processor clock cycle frequency and the overall speed of a machine. The RISC concept resulted from
improvements in programming languages, compiler technology, and memory size. The HP PA-RISC,
Sun SPARC, IBM Power PC, MIPS, and DEC Alpha machines are examples of RISC architectures.
Architecture models allowing multiple instructions to issue in a clock cycle are VLIW (very long
instruction word). VLIWs issue a fixed number of operations conveyed as a single long instruction and
place the responsibility of creating the parallel instruction packet on the compiler. Early VLIW processors
suffered from code expansion due to instructions. Examples of VLIW technology are the Multiflow Trace
and Cydrome Cydra machines. EPIC (explicitly parallel instruction computing) is similar in concept to
VLIW in that both use the compiler to explicitly group instructions for parallel execution. In fact, many
of the ideas for EPIC architectures come from previous RISC and VLIW machines. In general, the EPIC
concept solves the excessive code expansion and scalability problems associated with VLIW models by
not completely eliminating its functionality. Also, the trend of compiler controlled architecture mecha-
nisms are generally considered part of the EPIC-style architecture domain. The Intel IA-64, Philips
Trimedia, and Texas Instruments’ C6X are examples of EPIC machines.

42.5 Instruction Level Parallelism

Modern processors are being designed with the ability to execute many parallel operations at the instruc-
tion level. Such processors are said to exploit ILP (instruction-level parallelism). Exploiting ILP is
recognized as a new fundamental architecture concept in improving microprocessor performance, and
there are a wide range of architecture techniques that define how an architecture can exploit ILP.

Dynamic Instruction Execution
A major limitation of pipelining techniques is the use of in-order instruction execution. When an
instruction in the pipeline stalls, no further instructions are allowed to proceed to insure proper execution
of in-flight instruction. This problem is especially serious for multiple issue machines, where each stall
cycle potentially costs work of multiple instructions. However, in many cases, an instruction could execute
properly if no data dependence exists between the stalled instruction and the instruction waiting to
execute. Static scheduling is a compiler-oriented approach for scheduling instructions to separate depen-
dent instructions and minimize the number of hazards and pipeline stalls. Dynamic scheduling is another
approach that uses hardware to rearrange the instruction execution to reduce the stalls. The concept of
dynamic execution uses hardware to detect dependences in the in-order instruction stream sequence and
rearrange the instruction sequence in the presence of detected dependences and stalls.

©2002 CRC Press LLC