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FIGURE 42.12 Instruction sequence: (a) traditional execution, (b) speculative execution.

signals to be detected when the original execution does reach the original location of the load. When the
other path of branch’s execution is taken, such silent signals are meaningless and can be ignored. Using
this mechanism, the load can be placed above all existing control dependences, providing the compiler
with the ability to hide load latency. Details of compiler speculation can be found in Ref. 9.

42.6 Industry Trends

The microprocessor industry is one of the fastest moving industries today. Healthy demands from the
market have stimulated strong competition, which, in turn, have resulted into great technical innovations.

Computer Microprocessor Trends
The current trends in computer microprocessors include deep pipelining, high clock frequency, wide
instruction issue, speculative and out-of-order execution, predicated execution, natural data types, large
on-chip caches, floating point capabilities, and multiprocessor support. In the area of pipelining, the Intel
Pentium II processor is pipelined approximated twice as deeply as its predecessor Pentium. The deep
pipeline has allowed the clock Pentium II processor to run at a much higher clock frequency than Pentium.
In the area of wide instruction issue, the Pentium II processor can decode and issue up to three X86
instructions per clock cycle, compared to the two-instruction issue bandwidth of Pentium. Pentium II
has dedicated a very significant amount of chip area to branch target buffer, reservation station, and
reorder buffer to support speculative and out-of-order execution. These structures together allow the
Pentium II processor to perform much more aggressive, speculative, and out-of-order executions than
Pentium. In particular, Pentium II can coordinate the execution of up to 40 X86 instructions, which is
several times larger than Pentium.
In the area of predicated execution, Pentium II supports a conditional move instruction that was not
available in Pentium. This trend is furthered by the next generation IA-64 architecture where all instructions
can be conditionally executed under the control of predicate registers. This ability will allow future
microprocessors to execute control intensive programs much faster than their predecessors.
In the area of data types, the MMX instructions from Intel have become a standard feature of all
X86 microprocessors today. These instructions take advantage of the fact that multimedia data items are
typically represented with a smaller number of bits (8–16 bits) than the width of an integer data path
today (32–64 bits). Based on an observation, the same operation is often repeated on all data items in
multimedia applications—the architects of MMX specify that each MMX instruction performs the same
operation on several multimedia data items packed into one integer word. This allows each MMX
instruction to process several data items simultaneously to achieve significant speed-up in targeted ap-
plications. In 1998, AMD proposed the 3DNow! instructions to address the performance needs of 3-D

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