Page 1141 - The Mechatronics Handbook

graphics applications. The 3DNow! instructions are designed based on the concept that 3-D graphics
data items are often represented in single precision floating-point format and they do not require the
sophisticated rounding and exception handling capabilities specified in the IEEE Standard format. Thus,
one can pack two graphics floating-point data into one double-precision floating-point register for more
efficient floating-point processing of graphics applications. Note that MMX and 3DNow! are similar in
concepts applied to integer and floating-point domains.
In the area of large on-chip caches, the popular strategies used in computer microprocessors are either
to enlarge the first-level caches or to incorporate second-level and sometimes third-level caches on-chip.
For example, the AMD K7 microprocessor has a 64-KB first-level instruction cache and a 64-KB first-
level data cache. These first-level caches are significantly larger than those found in the previous gener-
ations. For another example, the Intel Celeron microprocessor has a 128-KB second level combined
instruction and data cache. These large caches are enabled by the increased chip density that allows many
more transistors on the chip. The Compaq Alpha 21364 microprocessor has both: a 64-KB first-level
instruction cache, a 64-KB first-level data cache, and a 1.5-MB second-level combined cache.
In the area of floating-point capabilities, computer microprocessors, in general, have a much stronger
floating-point performance than their predecessors. For example, the Intel Pentium II processor achieves
several times the floating-point performance improvements of the Pentium processor. For another exam-
ple, most RISC microprocessors now have floating-point performances that rival supercomputer CPUs
built just a few years ago.
Due to the increasing demand of multiprocessor enterprise computing servers, many computer micro-
processors now seamlessly support cache coherence protocols. For example, the AMD K7 microprocessor
provides direct support for seamless multiprocessor operation when multiple K7 microprocessors are
connected to a system bus. This capability was not available in its predecessor, the AMD K6.
Embedded Microprocessor Trends

There are three clear trends in embedded microprocessors. The first trend is to integrate a DSP core with
an embedded CPU/controller core. Embedded applications increasingly require DSP functionalities such
as data encoding in disk drives and signal equalization for wireless communications. These functionalities
enhance the quality of services of their end computer products. At the 1998 Embedded Microprocessor Forum,
ARM, Hitachi, and Siemens all announced products with both DSP and embedded microprocessors. 10
Three approaches exist in the integration of DSP and embedded CPUs. One approach is to simply have
two separate units placed on a single chip. The advantage of this approach is that it simplifies the develop-
ment of the microprocessor. The two units are usually taken from existing designs. The software develop-
ment tools can be directly taken from each unit’s respective software support environments. The
disadvantage is that the application developer needs to deal with two independent hardware units and two
software development environments. This usually complicates software development and verification.
An alternative approach to integrating DSP and embedded CPUs is to add the DSP as a co-processor
of the CPU. This CPU fetches all instructions and forwards the DSP instructions to the co-processor.
The hardware design is more complicated than the first approach due to the need to more closely interface
the two units, especially in the area of memory accesses. The software development environment also
needs to be modified to support the co-processor interaction model. The advantage is that the software
developers now deal with a much more coherent environment.
The third approach to integrating DSP and embedded CPUs is to add DSP instructions to a CPU
instruction set architecture. This usually requires brand-new designs to implement the fully integrated
instruction set architecture.
The second trend in embedded microprocessors is to support the development of single-chip solutions
for large-volume markets. Many embedded microprocessor vendors offer designs that can be licensed and
incorporated into a larger chip design that includes the desired I/O peripheral devices and application-
specific integrated circuit (ASIC) design. This paradigm is referred to as system-on-a-chip design. A
microprocessor that is designed to function in such a system is often referred to as a licensable core.

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