Page 63 - Wire Bonding in Microelectronics

42 Cha pte r T w o

In some cases, after bonding, the extending wire tail is peeled back as
a NDPT. This author is not aware of any published pa pers on this
method of bonding, and most of the equipment still in use is well
over 20 years old.

2.8 Major Chip Interconnection Alternatives
to Wire Bonding (Flip Chip and TAB)
As the off-chip speed increases and the bond pitch decreases, the
inductance and crosstalk of wire bonds limits their use (see Sec. 10.6).
Also, some high-silicon-density requirements cannot be met with
wire-bond interconnections. As the chip-power increases along with
lower operating voltage (down to one volt) and finer pitch, wire
bonds will not be able to carry the required current. Some projections
state that individual high-performance chips will draw over 100 A,
requiring hundreds of 25 µm diameter wire bonds just to distribute
the power. Also, as the I/O (input/output) pad-pitch decreases and
the number of peripheral pads increases, at some point area-array
pads will be required for interconnections. ITRS [2-69] projections
predict the finest wire-bondable pitch that can be achieved (at high
bond yields and adequate current carrying capacity), will be some-
where between 20 and 25 µm in single-row peripheral bond pads.
(Multiple rows, called area array bonding, over 4 µm deep, are pos-
sible with modern autobonders, but crosstalk can limit performance.)
At some point, a change to flip chip (C4, microballs, conductive poly-
mers, etc.) or some as yet undiscovered technology will be required
to solve future I/O interconnection limitations.
The most obvious alternatives to wire bonding are some varia-
tion of flip-chip interconnections. A thorough discussion of these
technologies and their many variations is beyond the scope of this
wire-bonding book, but some brief comments and comparisons are
described further in this chapter.

2.8.1 Flip Chip

Solder Ball Flip Chip
The most used, advanced interconnection alternative to wire bond-
ing is the flip chip (called C4, Controlled Collapse Chip Connection
or just FC). See Ref. [2-70]. This technology was invented in the mid
1960s at IBM. It has the lowest possible inductance per lead, ~0.05 to
0.1 nH (compared to ~1 nH/m for 25 mm diameter wire) and thus
the highest frequency response as well as the lowest crosstalk and
simultaneous switching noise. Flip chips also offer the highest pack-
aged Si density. They can be “tiled” as close together as 125 µm (5 mils)
on ceramic substrates in hermetic packages. For laminate substrates