Page 359 - ARM 64 Bit Assembly Language

Advanced SIMD instructions 349

addw Vector add wide,
sub Vector integer subtract,
fsub Vector floating point subtract,
qsub Vector saturating subtract,
subl Vector subtract long, and
subw Vector subtract wide.

10.6.1.1 Syntax

<op> Vd.T, Vn.T, Vm.T
<op> Dd, Dn, Dm
f<op> Vd.T, Vn.T, Vm.T
sq<op> Vd.T, Vn.T, Vm.T
uq<op> Vd.T, Vn.T, Vm.T
<sop>l{2} Vd.Td, Vn.Ts, Vm.Ts
<sop>w{2} Vd.Td, Vn.Td, Vm.Ts

• <op> can be add or sub.
• If double word registers are specified (Dd, Dn, Dm) then the operation is a simple add or
subtract of scalar 64-bit integer values, and not a vector operation.
• The valid choices for T are given in the following table:

Opcode Valid Values for T
<op> 8b, 16b, 4h, 8h, 2s, 4s,or 2d
f<op> 2s, 4s, 2d
(s|u)q<op> 8b, 16b, 4h, 8h, 2s, 4s, 2d

• <sop> can be uadd, sadd, usub,or ssub.
• If the modifier 2 is present, then the operation is performed using the upper 64 bits of the
registers holding the narrower elements.
• The valid choices for Td/Ts are given in the following table:

Opcode Valid Values for Td/Ts
<sop>l 8h/8b, 4s/4h, 2d/2s
<sop>l2 8h/16b, 4s/8h, 2d/4s
<sop>w 8h/8b, 4s/4h, 2d/2s
<sop>w2 8h/16b, 4s/8h, 2d/4s