Page 361 - ARM 64 Bit Assembly Language

Advanced SIMD instructions 351

10.6.2 Vector add and subtract with narrowing

These instructions add or subtract the corresponding elements of two vectors and narrow the
resulting elements by taking the upper (most significant) half:

addhn Vector add and narrow,
raddhn Vector add, round, and narrow,
subhn Vector subtract and narrow, and
rsubhn Vector subtract, round, and narrow.

The results are stored in the corresponding elements of the destination register. Results can be
optionally rounded instead of truncated.

10.6.2.1 Syntax

{r}<op>hn{2} Vd.Td, Vn.Ts, Vm.Ts

• <op> is either add or sub.
• If r is present, then the result is rounded instead of truncated.
• If 2 is present, then the upper 64 bits of the destination vector are used.
• The valid choices for Td/Ts are given in the following table:

Opcode Valid Values for Td/Ts
r<op>hn 8b/8h, 4h/4s, 2s/2d
r<op>hn2 16b/8h, 8h/4s, 4s/2d

10.6.2.2 Operations

Name Effect Description
{r}<op>hn shif t ← size ÷ 2 The operation is applied to corre-
if r is present then sponding elements of Vn and Vm.
x ← Vn[]<op>Vm[] The results are optionally rounded,
Vd[] ← x shif t ≺ then narrowedbytakingthe most
else significant half, and stored in the

x ← Vn[]<op>Vm[] corresponding elements of Vd.
Vd[] ← x shif t ≺
end if
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