Page 365 - ARM 64 Bit Assembly Language

Advanced SIMD instructions 355

faba Vector floating point absolute difference and accumulate,
abal Vector absolute difference and accumulate long, and
abdl Vector absolute difference long.
The long versions can be used to prevent overflow.

10.6.5.1 Syntax
(s|u)<op> Vd.T, Vn.T, Vm.T
fabd Vd.Tf, Vn.Tf, Vm.Tf
fabd Fd, Fn, Fm
(s|u)<op>l{2} Vd.Td, Vn.Ts, Vm.Ts

• <op> is either aba or abd.
• When a scalar register is specified (F is S or D), a scalar operation is performed instead of
a vector operation.
• If 2 is present, then the upper 64 bits of the source registers are used.
• T must be 8b, 16b, 4h, 8h, 2s,or 4s.
• Tf must be 2s, 4s,or 2d.
• Td/Ts must be one of 4s/8h, 8h/16b,or 2d/4s.
• The valid choices for Td/Ts are given in the following table:

Opcode Valid Types for Td/Ts
(s|u)<op>l 8h/8b, 4s/4h, 2d/2s
(s|u)<op>l2 8h/16b, 4s/8h, 2d/4s

10.6.5.2 Operations

Name Effect Description
{f}abd Vd[] ← |Vn[] − Vm[]| Subtract corresponding elements
and take the absolute value.
(s|u)aba Vd[] ← Vd[] + |Vn[] − Vm[]| Subtract corresponding elements
and take the absolute value. Accu-
mulate the results.
(s|u)abdl Vd[] ← |≺Vn[] − ≺Vm[] | Extend and subtract corresponding
elements, then take the absolute
value.
(s|u)abal Vd[] ← Vd[]+ Extend and subtract corresponding
|≺Vn[] − ≺Vm[] | elements, then take the absolute
value and accumulate the results