Page 363 - ARM 64 Bit Assembly Language
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Advanced SIMD instructions 353
10.6.3.2 Operations
Name Effect Description
(s|u)hadd Vd[] ← (Vn[] + Vm[]) 1 The corresponding elements of
Vn and Vm are added together. The
results are shifted right one bit
and stored in the corresponding
elements of Vd.
(s|u)rhadd Vd[] ← Vn[] + Vm[] 1 The corresponding elements of
Vn and Vm are added together. The
Results are rounded, then shifted
right one bit and stored in the cor-
responding elements of Vd.
(s|u)hsub Vd[] ← (Vn[] − Vm[]) 1 The elements of Vn are subtracted
from the corresponding elements
of Vm. Results are shifted right one
bit and stored in the corresponding
elements of Vd.
10.6.3.3 Examples
1 srhadd v1.16b,v6.16b,v8.16b // Add elements and divide by 2
2 uhsub v1.4h,v6.4h,v8.4h // Subtract and divide by 2
10.6.4 Add elements pairwise
These instructions add vector elements pairwise:
addp Vector add pairwise,
addlp Vector add long pairwise, and
adalp Vector add and accumulate long pairwise.
The long versions can be used to prevent overflow.
10.6.4.1 Syntax
addp Vd.T, Vn.T, Vm.T
faddp Vd.Tf, Vn.Tf, Vm.Tf
(s|u)addlp Vd.Td, Vn.Ts
(s|u)adalp Vd.Td, Vn.Ts
