Page 366 - ARM 64 Bit Assembly Language
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356 Chapter 10
10.6.5.3 Examples
1 uabd v0.8b,v1.8b,v2.8b // unsigned absolute difference
2 fabd v3.4s,v6.4s,v8.4s // floating point absolute difference
3 uaba v0.8b,v1.8b,v2.8b // unsigned absolute difference and
4 // accumulate
5 sabdl v0.2d,v1.2s,v2.2s // signed absolute difference-long result
6 sabdl2 v0.2d,v1.4s,v2.4s // signed absolute difference-use upper
7 // half of v1 and v2 - long result
10.6.6 Absolute value and negate
These operations compute the absolute value or negate each element in a vector:
abs Vector absolute value,
neg Vector negate,
fabs Vector floating point absolute value, and
fneg Vector floating point negate,
The saturating versions can be used to prevent overflow.
10.6.6.1 Syntax
{sq}<op> Vd.T, Vn.T
f<op> Vd.Tf, Vn.Tf
• <op> is either abs or neg.
• T may be 8b, 16b, 4h, 8h, 2s, 4s,or 2d.
• Tf may be 2s, 4s,or 2d.
10.6.6.2 Operations
Name Effect Description
{sq}abs if sq is present then Copy absolute value of each ele-
Vd[] ← |Vm[]| ment of Vm to the corresponding
else element of Vd, optionally saturating
Vd[] ← |Vm[]| the result.
end if
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