Page 262 - DSP Integrated Circuits

6.7 Equivalence Transformations 247

Assume here that the data word length is 12 bits and that the filter is
implemented with bit-serial arithmetic using so-called true single-phase clock
(TSPC}. This type of logic is modeled by model 1, i.e., the latencies for addition,
subtraction, and multiplication in this logic style are one clock cycle longer that the
theoretical minimum. Thus, we have in this case T a^ = 1 clock cycle and T mui t = 4
clock cycles.
The delay (latency) due to the arithmetic operations in the recursive loop is

and the number of delay elements in the loop is N{ = 2. Hence, we get the iteratior
period bound

and

where fcL is the clock frequency. The bit-serial implementation must therefore
have a clock frequency of at least 105 MHz to be as fast as the implementation
using bit-parallel, redundant arithmetic. This represents a relatively modest clock
frequency.
The iteration period bound for this algorithm using a static logic style (i.e.,
model 0, having minimum latencies T a^ = 0 clock cycle and T mui t = 3 clock
cycles) is

It is important to note that the length of the clock cycles are different between
the two models. In practice, the implementation corresponding to model 1 may be
the fastest, because of shorter propagation paths between the memory elements.

6.7 EQUIVALENCE TRANSFORMATIONS

Computation graphs describing DSP algorithms usually contain only shift-invari-
ant operations or processes. Hence, the ordering of an operation in series with a
memory element may be changed. This simple property is the basis for scheduling
operations that aim at minimizing the amount of resources required to implement
the algorithm. Scheduling will be discussed in more detail in Chapter 7. Another
related transformation, also based on interchanging shift-invariant operators, is
pipelining. We will discuss various forms of pipelining in section 6.8.
In some cases operations in DSP algorithms represent associative, distribu-
tive, or commutative operators [5, 20-22, 25]. In this section we will show how
these properties can be exploited to improve the computational properties of an
algorithm. Of course, the maximum sample rate of a fully specified recursive algo-
rithm is fixed and cannot be improved. However, an algorithm can in some cases
be used as a starting point to derive another algorithm that is faster.