Page 327 - DSP Integrated Circuits

312 Chapter? DSP System Design

Figure 7.39 Maximally fast schedule for the second-order section

sections, which will require additional equalizing delays in the schedule to
lengthen the scheduling period. Second, each section can be scheduled to be maxi-
mally fast, and then the clock period can be increased to match the bandwidths.
The obvious choice is the first alternative, since the second alternative requires
excessive hardware in terms of multiple clocks, bit-buffers, and multiplexers-
demultiplexers between sections with different m in order to adjust the number of
sample inputs.
Additional equalizing delays should preferably be inserted in cuts with few
branches to minimize the amount of extra storage. Suitable locations for addi-
tional delay in the preceding schedules are between the processor sets NI, since
these cuts only contain the branches corresponding to the loops in the algorithm.
Since the regular structure of lattice wave digital filters also is found in the
maximally fast schedule, it should be a reasonably simple task to develop software
tools for automatic synthesis of such filters directly from the transfer function.