Page 360 - DSP Integrated Circuits
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7.11 FFT Processor, Cont. 345
Figure 7.89 Exclusion graph for PEs for a four-point FFT
trates the derivation of the exclusion graph for a four-point FFT. The data with
index 1 after stage 1 is assigned to one of the memories. If the butterflies in rows 0
and 1 were assigned to the same PE, this memory would have to communicate
with both the top and the bottom inputs of the PE. This is denoted with the dashed
