Page 365 - DSP Integrated Circuits
P. 365
350 Chapter 7 DSP System Design
[4] Crochiere R.E.: Digital Network Theory and Its Application to the Analysis
and Design of Digital Filters, PhD Diss., Dept. Elec. Eng., MIT, Cambridge,
MA., May 1974.
[5] Crochiere R.E. and Oppenheim A.V.: Analysis of Linear Digital Networks,
Proc. IEEE, Vol. 63, No. 4, pp. 581-595, April 1975.
[6] Davidson S., Landskov D., Shriver B.D., and Mallett P.W.: Some Experiments
in Local Microcode Compaction for Horizontal Machines, IEEE Trans, on
Computers, Vol. C-30, No. 7, July 1981.
[7] Granski M., Koren I., and Silberman G.M.: The Effect of Operation
Scheduling on the Performance of a Data Flow Computer, IEEE Trans, on
Computers, Vol. C-36, No. 9, Sept. 1987.
[8] Heemstra de Groot S.M. and Herrmann O.E.: Evaluation of Some Multi-
processor Scheduling Techniques of Atomic Operations for Recursive DSP
Filters, Proc. European Conf. on Circuit Theory and Design, pp. 400-404,
Brighton, UK, Sept. 5-8,1989.
[9] Heemstra de Groot S.M. and Herrmann O.E.: Rate-Optimal Scheduling of
Recursive DSP Algorithms Based on the Scheduling-Range Chart, Proc.
IEEE Intern. Symp. on Circuits and Systems, pp. 1805—1808, New Orleans,
LA, May 1-3,1990.
[10] Laarhoven van P.J.M. and Aarts E.H.L.: Simulated Annealing: Theory and
Applications, D. Reidel., 1987.
[11] Leung J.Y.-T.: A New Algorithm for Scheduling Periodic, Real-Time Tasks,
Algorithmica, No. 4, pp. 209-219,1989.
[12] Lee E.A. and Messerschmitt D.G.: Synchronous Data Flow, Proc. IEEE, Vol.
75, No. 9, pp. 1235-1245, Sept. 1987.
[13] Lee J.-H., Hsu Y.-C., and Lin Y.-L.: A New Integer Linear Programming
Formulation for the Scheduling Problem in Data Path Synthesis, Proc. IEEE
Intern. Conf. on Computer-Aided Design, pp. 20—23, Santa Clara, CA, Nov. 5—
9,1989.
[14] McFarland M.C., Parker A.C., and Camposano R.: Tutorial on High-Level
Synthesis, 25th ACM/IEEE Design Automation Conf, pp. 330-336,1988.
[15] Nordhamn E.: Design of an Application-Specific FFT Processor, Linkoping
Studies in Science and Technology, Thesis No. 324, Linkoping University,
Sweden, 1992.
[16] Otten R.H.J. and van Ginneken L.P.P.P.: The Annealing Algorithm, Kluwer
Academic Pub., 1989.
[17] Paulin P.G. and Knight J.P.: Force-Directed Scheduling for the Behavioral
Synthesis of ASICs, IEEE Trans, on Computer-Aided Design, Vol. 8, No. 6,
June 1989.
[18] Paulin P.G. and Knight J.P.: Scheduling and Binding Algorithms for High-
Level Synthesis, Proc. 26th ACM/IEEE Design Automation Conf, pp. 1-6,
Las Vegas, NV, June 25-29,1989.
[19] Paulin P.G. and Knight J.P.: Algorithms for High-Level Synthesis, IEEE
Design and Test of Computers, pp. 18—31, Dec. 1989.
[20] Renfors M. and Neuvo Y: The Maximum Sample Rate of Digital Filters
under Hardware Speed Constraints, IEEE Trans, on Circuits and Systems,
CAS-28, No. 3, March 1981, pp. 196-202.
[21] Rutenbar R.A.: Simulated Annealing Algorithms: An Overview, IEEE
Circuits and Devices Magazine, pp. 19—26, Jan. 1989.