Page 366 - DSP Integrated Circuits
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7.12 DCT Processor, Cont.                                            351

        [22] Schwartz D.A. and Barnwell III T.P.: Cyclo-Static Multiprocessor Scheduling
             for the Optimal Realization of Shift-Invariant Flow Graphs, Proc. Inter. Conf.
             on Acoustics, Speech and Signal Processing, Tampa, FL, Vol. 3, pp. 1384-
             1387, March 26-29,1985.
        [23] Schwartz D.A. and Barnwell III T.P.: Cyclo-Static Solutions: Optimal
             Multiprocessor Realizations of Recursive Algorithms, VLSI    Signal
            Processing, II, IEEE Press, 1986.
        [24] Wanhammar L., Afghahi M., and Sikstrom B.: On Mapping of DSP
             Algorithms onto Hardware, IEEE Intern. Symp. on Circuits and Systems,
             ISCAS-88, pp. 1967-1970, Espoo, Finland, June 1988.
        [25] Wanhammar L., Sikstrom B., Afghahi M., and Pencz J.: A Systematic Bit-Serial
             Approach to Implement Digital Signal Processing Algorithms, Proc. 2nd Nordic
             Symp. on VLSI in Computers and Communications, Linkoping, June 2—4,1986.
        [26] Yuan J. and Svensson C.: High-Speed CMOS Circuit Technique, IEEE J. on
             Solid-State Circuits, Vol. SC-24, No. 1, pp. 62-70, Feb. 1989.


        PROBLEMS
         7.1 Consider a 16-point ST-FFT.
             (a) Determine which pairs of butterflies are computed in the two
                alternatives discussed in section 7.3.2.
             (b) Determine the range of the following indices: m, £]_, &uvs> &2> &2Ws> and p.
             (c) Show how the computations of these indices can be simplified.
             (d) What hannens if the index m is
                incremented in Gray-order?

         7.2 Modify the program in Box 7.2 so that four
             butterflies can be computed concurrently.
         7.3 Schedule the operations in the second-order
             filter shown in Figure P7.3 so that T mi n is
             reached.                                   Figure P7.3. Second-order
             (a) Assume T add = T mui t = I t.u.                 filter
             (b) Assume T muit = 3 T add and T add = I t.u.
         7.4 Assume that the adders have unit delay.
             The times taken for the multiplications are
             indicated in Figure P7.4. What is the
             minimum sample period? Sketch a possible
             scheduling of the PEs that yields a
             minimum iteration period assuming that
             the multipliers are nonpreemptive. How
             many PEs are needed and what is their
             degree of utilization?
         7.5 (a) Derive the computation graph for the
                maximally fast second-order section in
                direct form II.
             (b) Schedule the operations over one
                sample interval so that the number of
                concurrent operations is minimized.           Figure P7.4
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