Page 415 - DSP Integrated Circuits

400 Chapter 9 Synthesis of DSP Architectures

The new algorithm can be described by the state-space equations

where A, S, C, D, and v are matrices and vectors with dimensions M x M, M x 1,
1 x M, 1 x 1, and M x 1, respectively. In order to demonstrate this implementation
technique and some possible trade-offs, we explicitly write the matrix equations
for the special case M = 5, as shown in Equation (9.4):

Each new coefficient will essentially consist of a product of some of the
original coefficients. The new coefficient word length will therefore be proportional
to the sum of the word lengths of the coefficients in the products. Hence, the word
length will be excessively large for highly sequential algorithms since there will be
many more factors in the products. Highly parallel algorithms, on the other hand,
will have fewer factors and therefore a shorter word length.
Each of the left-hand variables can be computed using six vector-multipliers
and broadcasting the right-hand variables, as illustrated in Figure 9.15. Note that
the PEs work in parallel and the hardware structure is regular and modular. The
hardware structure can easily be multiplexed among several input signals. Such
applications are common in telephone systems where the cost for the multiplexed

Figure 9.15 Numerically equivalent implementation using vector-multiplier PEs