Page 474 - DSP Integrated Circuits

10.7 Finite State Machines (FSMs) 459

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PROBLEMS
10.1 Identify different hierarchical levels, as illustrated in Figure 10.1, for the
FFT processor.
10.2 What is the difference between latches and flip-flops? Also show that a D flip-
flop can be realized as two cascaded latches and determine their clocking.

10.3 Determine the type of flip-flop shown in Figure 10.12. Which edge of the
clock signal is active?
10.4 Suggest a logic circuit that implements a nonoverlapping two-phase clock.

10.5 Derive the complete 2-bit serial: adder in Example 10.1 with the appropriate
input and output signals.
10.6 Use the look-ahead method to double the throughput of a bit-serial
subtracter.