Page 509 - DSP Integrated Circuits

494 Chapter 11 Processing Elements

For a 12-bits word length, the optimal multipliers achieve an average reduc-
tion of 16% in the number of adders required over CSDC. Note, however, that for a
particular multiplicand the reduction may be much larger.
In digital niters, FFTs, etc., it is in practice sufficient to use no more than five
additions, which can represent all coefficients with 16-bit word lengths and, of
course, many numbers corresponding to the longer word lengths.
In practice it may be efficient to once and for all generate and store a table of
the best alternative realizations for word length of interest—for example, up to 12
to 14 bits. When a search for favorable coefficient is performed, the cost can then
be obtained from this table.

EXAMPLE 11.9
Find possible graphs for realization of the mul-
tiplicand 75 using two or three adders/subtrac-
tors. Derive also the corresponding bit-serial
multiplication realization with the coefficient
75/128 from these graphs.
Figure 11.29 shows two alternative algo-
rithms for the integer 75. The first, which requires
three adders, corresponds to the realization

and the second alternative, which only requires
two adders, corresponds to

To derive the
graphs correspond-
ing to multiplication
with 75/128 we insert
a D flip-flop for every
power of 2 and scale
the output with
1/128 by moving the
binary point seven
positions to the left.
The resulting real-
izations are shown in
Figure 11.30.

Figure 11.30 Alternative realizations of multiplication with
the coefficient 75/128