Page 511 - DSP Integrated Circuits

496 Chapter 11 Processing Elements

EXAMPLE 11.10
Find possible graphs that simultaneously realize the multiplications

and

where Ci = 7 and c 2 = 106.
Figure 11.34 shows two
alternative realizations. In both
cases only three adder/subtrac-
tors are required.

Figure 11.34 Alternative graphs for
multiplication with 7 and 106

11.10 BIT-SERIAL SQUARERS

To derive a suitable algorithm for implementing a unit that computes the square
2
# of a bit-serial number x, we will first discuss the special case where x is a frac-
tional, unsigned binary number [46].

11.10.1 Simple Squarer
Since the square is to be computed in a bit-serial fashion, we need to decompose
the square into suitable bit components to find the necessary operations for com-
puting each bit in the wanted result. An n-bit, fractional, unsigned binary number
x is written as

Now, let the function /"represent the square of the number x—i.e.,

Then, the computation of f can be carried out in n iterations by repeatedly
squaring the sum of the most significant bit of a number and the other bits of that
number. In the first step, f\ = f(x) is decomposed into the square of the most signif-
icant bit of x with a rest term and a remaining square fy.