Page 545 - DSP Integrated Circuits

530 Chapter 11 Processing Elements

11.25 (a) Find a bit-serial multiplier that implements the coefficient

(b) Determine the normal serial/parallell multiplier for the same
coefficient value.
(c) Determine the relationship between the two multiplier structures.

11.26 Redo Example 6.7, but include appropriate control signals as well.
11.27 Derive bit-parallel implementations of the control processes used in the
FFT processor. Discuss trade-offs between the bit-serial and bit-parallel
versions.
11.28 Conversion between RGB and YCbCr digital color video image formats can
be performed by the following transformations:
R = Y + 350 Cr/256 - 175/256
G = Y- 86 C6/256 - 178 Cr/256 + 132/256
B = Y + 444 C6/256 - 222/256
and
Y = (77 R + 150 G + 29 £)/256
Cb = (-44 R - 87 G + 131 B)/256 + 128/256
Cr = (131R - 110 G - 21 B)/256 + 128/256
The color components are quantized to 8 bits. Derive an implementation
based on
(a) Bit-serial multipliers
(b) Distributed arithmetic
(c) Compare the two implementations.
11.29 Suggest a logic realization of error-feedback for both a serial/parallell
multiplier and a distributed arithmetic PE. Can the input, S, in Figure
11.49 be used? What are the potential advantages of such an approach?

11.30 Derive a VHDL description of a serial/parallell multiplier.
11.31 Derive an implementation of the fast 1-D DCT using serial/parallell
multipliers and compare the result with the implementation using
distributed arithmetic.
11.32 Derive an implementation of the 1-D DCT using column symmetry and
distributed arithmetic.

11.33 Suggest a bit-parallel implementation of the complex multiplier, which is
based on distributed arithmetic, and compare it to the version used in the
case study.