Page 542 - DSP Integrated Circuits

Problems 527

required in a bit-serial isomorphic implementation. W^ = 20 bits and
a =0.375.
(b) Determine the number of D flip-flops and bit-serial adders (subtracters)
required to implement the multiplication using a simplified S/P
multiplier.
(c) Determine the maximal sampling frequency when the full-adders can be
clocked at 400 MHz.
(d) Sketch the attenuation for the filter.
11.10 (a) Modify the two-port adaptor in
order to implement the
multiplications by -1 that may
appear in lattice wave digital
filters.
(b) Show that it is sufficient to
invert all bits, including the
sign bit, in the reflected waves
that exceed the signal range,
in order to suppress overflow
oscillations in wave digital
filters. Two's-complement
FigP11.9 Third-order lattice WDF
representation is used for the
signals.
11.11 Suggest a bit-serial PE for implementation of a product, x y, of two
variables. The external interface should be bit-parallel.
11.12 Suggest a bit-serial PE based on serial/parallell multipliers for
implementation of a

(a) Direct form FIR filter with fixed coefficients.
(b) Transposed direct form FIR filter with fixed coefficients.
11.13 Derive a bit-serial realization of both a series and parallel two-port adaptor.

11.14 Consider the sum of products

which shall be evaluated by a PE based on distributed arithmetic. The data
word length is Wj =17 bits, and the coefficients are

Suggest a block diagram for the PE and describe how it works. How many
bit-slices are required? Determine also the contents in the ROM.

11.15 Distributed arithmetic is used to compute:

where jc/ are variables and a; are fixed coefficients. The data word length is
Wd and the word length in the ROM is WRQM- Further we have Wj > WRQM-