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524 Chapter 11 Processing Elements
[13] Dempster A.G. and Macleod M.D.: Constant Integer Multiplication Using
Minimum Adders, IEE Proc. Circuits Devices Systems, Vol. 141, No. 5, pp.
407^13, Oct. 1994.
[14] Dempster A.G. and Macleod M.D.: Use of Minimum-Adder Multiplier Blocks
in FIR Digital Filters, IEEE Trans, on Analog and Digital Signal Processing,
Vol. 42, No. 9, pp. 569-577, Sept. 1995.
[15] Ercegovac M.D. and Lang T.: On-the-Fly Conversion of Redundant into
Conventional Representations, IEEE Trans, on Computers, Vol. C-36, No. 7,
pp. 895-897, July 1987.
[16] Ginderdeuren van J.J., De Man H.J., Goncalves N.F., and van Noije W.A.M.:
Compact NMOS Building Blocks and a Methodology for Dedicated Digital
Filter Applications, IEEE J. on Solid-State Circuits, Vol. SC-18, No. 3, pp.
306-316, June 1983.
[17] Hartly R.I. and Parhi K.K.: Digit-Serial Computation, Kluwer Academic
Pub., Boston, 1995.
[18] Hwang I.S. and Fisher A.L.: Ultra Fast Compact 32-Bit CMOS Adder in
Multi-Output Domino Logic, IEEE J. Solid-State Circuits, Vol. SC-24, pp.
358-369,1989.
[19] Hwang K.: Computer Arithmetic: Principles, Architecture, and Design, New
York, John Wiley & Sons, 1979.
[20] Ingelhag P., Jonsson B., Sikstrom B., and Wanhammar L.: A High-Speed Bit-
Serial Processing Element, ECCTD-89, pp. 162-165, Brighton, UK, Sept. 1989.
[21] Karlsson I.: True Single Phase Dynamic CMOS Circuit Technique, IEEE
Intern. Symp. on Circuits and Systems, ISCAS-88, pp. 475-478, Espoo,
Finland, June 1988.
[22] Koren I.: Computer Arithmetic Algorithms, Prentice Hall, Englewood Cliffs,
New Jersey, 1993.
[23] Li D.: Minimum Number of Adders for Implementing a Multiplier and Its
Application to the Design of Multiplierless Digital Filters, IEEE Trans, on
Circuits and Systems II, Vol. CAS-II-42, No. 7, pp. 453-460, July 1995.
[24] Li W.: A Fully Parallel Implementation of Distributed Arithmetic, IEEE
Intern. Symp. on Circuits and Systems, ISCAS-88, pp. 1511-1515, Espoo,
Finland, June 1988.
[25] Lindkvist H. and Andersson P.: Techniques for Fast CMOS-Based
Conditional Sum Adders, IEEE Intern. Conf. on Computer Design,
Cambridge, MA, pp. 626-635,1994.
[26] Lyon R.F.: Two's Complement Pipeline Multipliers, IEEE Trans, on
Communication, Vol. Com-24, No. 4, pp. 418-424, April 1976.
[27] Ma G.K. and Taylor F.J.: Multiplier Policies for Digital Signal Processing,
IEEE ASSP Magazine, Vol. 7, No. 1, pp. 6-20, Jan. 1990.
[28] Melander J., Widhe T, Sandberg P., Palmkvist K, Vesterbacka M., and
Wanhammar L.: Implementation of a Bit-Serial FFT Processor with a
Hierarchical Control Structure, Proc. European Conf. on Circuit Theory and
Design, ECCTD '95, Istanbul, Turkey, Aug. 1995.
[29] Nordhamn E.: Design of an Application-Specific FFT Processor, Linkoping
Studies in Science and Technology, Thesis, No. 324, Linkoping University,
Sweden, 1992.
[30] Peled A. and Liu B.: A New Hardware Realization of Digital Filters, IEEE
Trans, on Acoust, Speech, Signal Processing, Vol. ASSP-22, No. 6, pp. 456-
462, Dec. 1974.

