Page 538 - DSP Integrated Circuits

References 523

structure, the pixels that are multiplied by the same coefficient are added (or sub-
tracted). This reduces the number of terms in the remaining inner products by
N
/2
50%. The chip area is thereby reduced from O(2 ) to O(2^ ), which is a significant
reduction. In comparison, the area for the bit-serial adders is insignificant. Figure
11.58 shows a block diagram for the DCT PE.
A 2-D DCT for 16 x 16 pixels can be built using only one 1-D DCT PE which
itself consists of 16 distributed arithmetic units with N = 8. The TSPC-based
shift-accumulator in Figure 11.51 can be used to implement a distributed arith-
metic unit. The length of the shift-accumulator depends on the word length,
WROM, which depends on the coefficients in the vector-products. In this case we
assume that WRQM = W c +1 = 12 bits. The ROM corresponding to each bit-slice is
3
organized to have eight rows and 2^~ columns in order to have about the same
width as the bit-slices.
The area for a 1-D DCT PE is estimated to
2
A DCT « 16 A DA +A Wire » 16 • 0.246 • 1.3 mm - 5.2 mm 2
where we have assumed that the area reserved for wiring is about 30%.

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