Page 113 - Embedded Microprocessor Systems Real World Design

Hardware Design 2 3

Dynamic Bus Sizing

The previous chapter mentioned %bit versus 16-bit and 32-bit operations and the
need for hardware to support access to 16-bit or 32-bit data on a byte basis. Some
microprocessors provide for dynamic hus sizing in which the peripheral or memory
tells the CPU the bus width.
A typical device that implements dynamic bus sizing is the Motorola MC68HC16,
which is a microcontroller with external bus capability. As Figure 3.1 shows, the
MC68HC16 uses a bus interface similar to the 68000 but with two acknowledge
signals instead of one. An %bit peripheral or memory asserts -DSACKO to termi-
nate the cycle, and a 16-bit device asserts -DSACKl.
To simplify the CPU hardware, the MC68HC16 requires that %bit devices
connect to data-bus lines 8 through 15, whereas 16-bit devices use all 16 data
lines.

Fast Cycle Termination

Another feature implemented on the MC68HC16 is fast cycle termination. One
problem with any bus structure that requires an acknowledge for each cycle is that
for maximum speed, each peripheral must assert the acknowledge in a timely
fashion. The normally-not-ready structure imposes a speed penalty in integral
clocks for any peripheral that is slow to generate the acknowledge. Plus, as men-
tioned in the last chapter, every peripheral must have logic to generate an acknowl-
edge signal back to the CPU.
In some designs, you want bus speeds more like the normally-ready bus of
the Intel processors. The MC68HC16 provides a means for this in its internal
chip select unit. The chip select unit, in addition to providing chip select signals
to external devices, can also generate an acknowledge. This internal acknowledge

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