Page 116 - Embedded Microprocessor Systems Real World Design

Knowing this, you can eliminate the -RD and -WR signals (-DS on a
Motorola-style bus) and just synchronize everything to the processor clock. As long
as the peripheral knows what clock edge to use and meets the setup and hold-time
requirements, everything will work the same as if the strobe signals were there.
Figure 3.2B shows such a clock-synchronized bus. This example is based on the
timing for the Intel i960 microprocessor. The address and status signals are driven
onto the bus and the -ADS signal indicates a valid address. The address and status
signals include all the status signals, including the address lines, DMA indication,
-LOCK signal, and read/write signal. Essentially, everything the peripheral device
needs to determine what kind of bus cycle is being started is available while -ADS
is low.
The peripheral decodes the address and status signals, capturing them on the
rising clock edge that occurs while -ADS is low. Before the next rising clock edge
(-ADS has gone high), the peripheral places data on the data bus and the CPU
captures it on the rising clock edge. This scheme allows all the decoding logic to
be synchronous. The catch is that the decoding logic or the peripheral must keep
track of when the CPU expects data. The last cycle shown in Figure 3.2B illustrates
a bus cycle that is extended by a wait state. The peripheral (or the decoding logic)
must keep track of which clock it is on and drive the data lines on the right clock
edge.
Processors that support such a clock-based bus often provide a burst mode of
operation that is ideal for interfacing to burst-mode memories such as DRAM. The
i960 supports such a burst mode, as shown in Figure 3.2C. The first cycle looks like
the ones shown in Figure 3.2B, but subsequent cycles can transfer one word from
memory per clock cycle (assuming appropriate memory speed). Although not
shown in Figure 3.2C, the i960 has two additional address signals that are cycled
through when the burst mode is used, allowing up to four words to be accessed in
this mode.
The i960 also supports a pipelined mode. In this mode, each data transfer takes
two clock cycles, like the bus cycles in Figure 3.2B. However, the cycles overlap so
that while the CPU is reading data for one address, it is placing the address and
status information for the next bus cycle on the bus. This allows one word to be
transferred per clock cycle, just as in burst mode. Obviously, the decoding logic
must detect this condition, capturing the address/status information and enabling
the right peripheral or memory at the right time.
Intel is not the only manufacturer whose processors use a clock-synchronized
bus. The Motorola Power PC uses a bus that has different signal names but timing
that is very similar to the i960. Many processors have a clock-synchronized bus struc-
ture of some type.
Interfacing memory and peripherals to a clock-synchronized microprocessor is
similar to interfacing to an ordinary microprocessor. The same considerations apply
for setup, access, and hold timings. The differences are that, first, the times typi-

98 Embedded Microprocessm Systems