Page 118 - Embedded Microprocessor Systems Real World Design

Supports fast page and ED0 modes
Programmable refresh rate
Supports two banks of DRAM
Programmable row and column address size
Supports 256 K x 8 through 4 M x 16 DRAM
The device pins used to control the DRAM are, like most other external
functions on the chip, shared with the 1/0 ports. If you use the internal DRAM
controller, you must give up Port A on the device. However, the controller handles
all functions of interfacing to the DRAM, including address multiplexing and
refresh.
All DRAM controller features are programmed by writing to internal registers.
The MC68EZ328 supports about any DRAM you want to use, and even includes a
control bit that extends the -RAS precharge time for slower DRAM devices.
Although an onchip DRAM controller greatly simplifies microprocessor circuit
design, you still need to keep a few things in mind:
Choose a DRAM configuration (size x word width) that is supported by the CPU.
Make sure you can give up the pins needed for the DRAM interface.
Be sure the CPU supports the speed/setup time/modes of the DRAM you plan
to use. This includes features such as the extended -RAS precharge time of the
MC68EZ328.

Combination ICs

Most microprocessor designs that use external memory require both ROM/PROM
and SRAM. Many manufacturers produce ICs that combine both flash ROM and
SRAM in a single package. The Toshiba TH50VSF0302 is one such part, combin-
ing 1 M x 8 flash with 128K x 8 SRAM. The Toshiba part is designed for 2.7V to
3.3V operation, comes in a 48-pin ball grid array (BGA) package, and is available
with either a top or bottom boot block (see Chapter 2). The SRAM and flash share
a common data and address bus and the device has an access time of 100ns.
Toshiba and other manufacturers make other combination parts that include
bus widths up to 16 bits and memory densities to 2 MB (flash) and 512K (SRAM).
Interfacing these parts to a microprocessor is identical to interfacing other mem-
ories. You must keep in mind that the timing parameters for the RAM and flash
memory may not be the same. The Toshiba TH50VSF3680/3681, which has 8MB
of flash and 1MB of SRAM, is a typical example. The SRAM in this part has a
45 ns output enable access time, whereas the flash memory has 40 ns. The address
access times on the part are identical, 90ns.
The TH50VSF3680/3681 also has a configurable memory configuration feature.
Two pins determine the memory size versus bus width:

100 Embedded Micr@rocessor System