Page 114 - Embedded Microprocessor Systems Real World Design

-AS
ADDRESS BUS
DATA BUS
-DS
-DSACKO PERIPHERAL BEING ACCESSED
- ASSERTS EITHER DSACKO OR
-DSACKl DSACKI - NOT BOTH.
DSACKO ASSERTED - 8 BIT TRANSFER
DSACKl ASSERTED - 16 BIT TRANSFER

Figure 3.1
Dynamic Bus Sizing.

can be programmed to add from zero to 13 wait states to the cycle. Programming
zero wait states is the equivalent of a normally-ready bus, if the peripheral can
keep up.
Note that on the MC68HC16 and similar processors, the external acknowledge
signals are still monitored when the internal acknowledge is enabled. If you
program 13 wait states and some external device asserts one of the -DSACK signals
after 6 wait states, the CPU will terminate the cycle early. When designing with a
normally-not-ready bus and using internal acknowledge generators, be sure no
other peripherals inadvertently drive the acknowledge signals.

Bus Sizing at Reset

The MC68HC16 also allows the external bus to be set to either 8 or 16 bits when
the processor is reset. By tying two pins (-BERR and DATAl) high, the CPU will
configure the external data bus as 8 bits wide after a reset. This frees more pins on
the device for use as 1/0 signals.
Another Motorola microcontroller with a similar capability is the MC68EZ328.
This device, one of the Motorola Dragonball family of parts, has a single pin that
is tied low (8 bit) or high (16 bit) to indicate the external bus width. The CPU
reads the state of the pin at the trailing edge of the RESET input. On this partic-
ular device, the software can reprogram the functionality of the internal chip select
logic so that external accesses corresponding to specific chip select signals can be
either 8 or 16 bits wide. Like the MC68HC16, 8-bit transfers must use the upper
eight data bits (D8 through D15).
This programmable capability of the chip selects allows you to mix low-cost &bit
peripherals with higher-performance 1 &bit devices in the same design.

96 Embedded Macropocessar Systems