Page 117 - Embedded Microprocessor Systems Real World Design

cally are much shorter due to the higher clock rates. Second, the interface is syn-
chronous, so normally you will use some type of PLD, FPGA, or ASIC. The inter-
face logic must keep track of the type of bus cycle (burst, pipelined, and so on)
and insert wait states for peripherals that need them.
When interfacing to a synchronized bus, you are likely to find that you need a
wide variation in bus cycle times. You may use a fast DRAM or SDRAM that matches
the CPU speed, needing few or no wait states, and a slower peripheral that needs
three or four wait states. With a synchronized bus, the propagation delays in the
decoding logic become significant, although that is somewhat alleviated by the syn-
chronous nature of the design. Finally, to achieve maximum performance, the
interface logic must recognize and support special features of the bus, such as the
burst mode.
You will typically design a single logic block to control timing to the bus. This
logic block will take the address inputs (or outputs from an address decoder)
and generate appropriate wait states for all devices. Of course, you may have a dif-
ferent number of wait states for different memory ranges. When interfacing to a
16 or 32-bit processor, the appropriate byte read/write signals must be asserted
so that a write to one byte of a memory doesn’t change the other bytes in the
same word.
The most likely area for timing problems will be at the beginning and end of
cycles. Check the timing carefully to ensure that there aren’t any race conditions
caused by logic delays that will produce a brief pulse on one or more write signals.
Also check to ensure that bus release time at the end of a cycle, after all the logic
delays, is adequate to prevent bus contention at the beginning of the next cycle.
Processors such as the i960 series provide a signal such as -AS to indicate valid
address and status information. You can use ordinary transparent latches such as
the 74~x373 to hold this information stable, or you can embed the latches in a PLD
with the timing logic. In the case of the i960 CPU and a 74~x373 latch, the -AS
signal would need to be inverted before being applied to the latch.

Built-in Dynamic Ram Interface

Some sophisticated microcontrollers have built-in support for dynamic RAM. This
allows you to take advantage of the higher densities of DRAM without the cost and
board real estate required for an external DRAM controller. The Motorola
MC68EZ328 is one microcontroller that provides onchip support for DRAM. Fea-
tures of this device include:

Support for CASbefore-RAS refresh cycles and self-refresh mode
Supports 8- and l6bit DRAM

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