Page 224 - Embedded Microprocessor Systems Real World Design

Deciding how many processor subsystems to use and how to distribute the tasks
among them is usually based on three considerations:

Interdependence or modularity of the software.
Processor throughput.
Physical location.
Interdependent functions, such as positioning something using a stepper motor
and reading feedback from the position sensor, are well suited to sharing one
processor. In general, whatever arrangement minimizes the interprocessor com-
munication usually is a good distribution of functions. In the previous hypotheti-
cal example, it makes no sense for CPU 2 to handle communication from the host
and CPU 3 to handle communication to the host, unless the two information
streams are independent and unrelated.
Code complexity is an issue as well. If CPU 3 is eliminated from the example
and CPU 2 does both jobs, the software could become complex and difficult to
develop. For example, CPU 2 might need to work at a message level to talk to the
host, but getting continuous interrupts from sensors and motors makes the inter-
actions hard to predict. While CPU 2 might be able to handle the average process-
ing load, momentary peaks in taking care of motors might cause host data to be
missed or serviced late.
Physical location may determine the breakdown of tasks. CPU 3 may be located
remotely, near the motors. Even though CPU 2 is primarily a communication
processor (as opposed to device control processor), it might handle some minor
sensor or I/O device located nearby.
In a system that has optional configurations, a processor might be dedicated to
each option. The intelligence and cost to control the option (at least the low-level
control) goes with the option.

Communication Between Processors

For multiprocessor systems in which two or more processors are on the same board,
several methods of interprocessor communication are possible.

Communication Register
Figure 8.2 shows probably the simplest mechanism communication between two
processors on the same board. Data is clocked into an 8-bit register with tristate
outputs, such as a 74AC374 (or, of course, part of a PLD), using a decoded write
strobe from CPU 1. CPU 2 reads the data with a decoded read strobe. In this
scheme, the lower 7 bits in the register (DO through D6) are used to transfer data,

Multiprocessor Systems 205