Page 227 - Embedded Microprocessor Systems Real World Design

controller to read data from the register and put it in memory. Now the two DMA
controllers handle the transfer, typically at very high rates.
The problem with DMA-controlled transfers is this: How does CPU 2 know how
many bytes to transfer? Three solutions to this problem exist:

1. The first DMA technique is very simple. All transfers are a specified size, such
as 256 bytes. If the data to be transferred are shorter than that, it is padded out
(with zeros or some other constant value) to the block size.
2. The second technique involves a length byte. The first byte transferred by
CPU 1 is a length value. CPU 2 sets up its DMA controller to transfer 1 byte and
generate an interrupt when done. When the length byte is received, CPU 2 ser-
vices the interrupt and sets up the DMA controller to receive the specified
number of bytes. This method requires CPU 2 to service two interrupts for every
transfer.
3. The third technique requires a second interrupt path between the two proces
sors. CPU 2 sets up its DMA controller to transfer more than the maximum
number of bytes in an actual message. If the longest message is 64 bytes, then
CPU 2 sets up the DMA controller to transfer any value greater than 64 bytes.
CPU 1 sets up the DMA transfer and, when it is completed, notifies CPU 2 via
the separate interrupt path, CPU 2 reads the number of bytes transferred from
its DMA controller and then processes the received data. Note that the CPU
2 DMA controller will never generate an interrupt since it never transfers
the number of bytes programmed. You can use the DMA technique even if only
one processor supports DMA. The non-DMA processor can poll the register to
see when data are available. The speed is no higher than a polled register
approach, but whichever processor has DMA is relieved of the need to poll for
each byte.
Figure 8.4 illustrates a variation of this DMA method. This was designed for a
dual430188 application where CPU 1 had both DMA channels used for something
else. The DMA channels of CPU 2 were used for data transfer. This scheme uses
two &bit registers for bidirectional communication. Register 1 transfers data from
CPU 1 to CPU 2, and Register 2 transfers data from CPU 2 to CPU 1. The register
full bit for Register 1 drives DMA channel 0 on CPU 2 and the register empty bit
on Register 2 drives DMA channel 1 on CPU 2.
In addition, there is one interrupt from CPU 1 to CPU 2 and one from CPU 2
to CPU 1. The CPU 1 to CPU 2 interrupt is set by CPU 1 and cleared by CPU 2.
The other interrupt is set by CPU 2 and cleared by CPU 1. Both interrupts are avail-
able as status bits to both CPUs. Interrupt set and clear, of course, are decoded
read/write strobes.
The sequence of events for transferring data from the CPU 1 to CPU 2 is as
follows:

208 Embedded Microprocessor Systems