Page 231 - Embedded Microprocessor Systems Real World Design

FIFO buffers replace the register, with one CPU writing the FIFO buffer and the
other CPU reading the FIFO buffer. The FIFO buffer holds the data, allowing CPU
2 to read the data in order at its convenience. Most FIFO buffers have a pin that
tells when the FIFO buffer is empty. This can be monitored to determine when
data are in the FIFO buffer (not empty = data available).
A FIFO can reduce the impact of communication on both CPUs. As long as
messages are only a fraction of the FIFO depth, the sender can just write the
entire message to the FIFO and go on about its business. The receiver can read the
entire message or as many bytes as are available when it discovers that the FIFO is
not empty.
One drawback to the FIFO is that the sender does not have byte-by-byte indica-
tion that the receiver has taken the message. If the receiver falls behind or even
stops, the FIFO may have to get completely full before the sender knows the data
were read. One way around this is to use a message-level indication: The sender
sends an entire message at a time but doesn't send another message until the FIFO
goes empty.

Dual-Port RAM (DPRAM)

In cases in which a lot of data must be transferred between two processors, a dual-
port RAM (DPRAM) is common. DPRAM is shared between two processors. If both
processors want to access the RAM at the same time, one has to wait until the other
is finished.
Some DPRAM ICs handle arbitration internally. These devices have a signal to
each processor to request a wait state for arbitration, or they use a synchronous dual-
port memory architecture that permits simultaneous access by both processors. The
709089 from Integrated Device Technologies (IDT) is a 64K x 8 dual-port RAM.
The IDT '1052 is a 2K x 8 four-port device that can allow four processors to com-
municate using a common RAM area.
One drawback to using synchronous DPRAM ICs is possible data corruption.
If one processor writes to a location while the other is reading, the write may not
be completed correctly or the read data may be corrupted. For cost-sensitive
designs, an inexpensive way to produce a DPRAM is to use the bus hold capability
of one CPU.
The block diagram in Figure 8.6 illustrates a means to implement the hold based
DPRAM. This example uses two Intel-style processors, such as the 80188, but the
concept can be adapted to any processor that has bushold capability.
CPU 1 has an address decoder that selects its local RAM, ROM, I/O, and access
to the other processor. For simplicity, the CPU 1 RAM, ROM, and 1/0 are not
shown.

212 Embedded Microprocessor Systems