Page 233 - Embedded Microprocessor Systems Real World Design

The PLD equations for this are as follows:

// PIN DESCRIPTIONS
// !XWR,!XRD: EXTERNAL PROCESSOR READ AND WRITE STROBES.
// !XSEL: ADDR DECODE FROM EXTERNAL PROCESSOR.
// HLDA: FROM LOCAL 188.
// DL140: 140 NS OUTPUT OF DELAY LINE
// DUO: 40 NS OUTPUT OF DELAY LINE
// DIR: DIRECTION CONTROL FOR ACT245 BUS BUFFER.
// 0 = READ FROM LOCAL BUS TO EXERNAL BUS.
// !DEN ENABLE FOR ACT245 BUS BUFFER
// !AEN: ENABLES ADDRESS BUPF'ERS FROM EXTERNAL ADDR BUS
// TO LOCAL ADDR BUS.
// !LRD: READ STROBE TO LOCAL BUS
// !LWR: WRITE STROBE TO LOCAL BUS
// HOLD: TO LOCAL 188.
// !XWAIT: TO EXTERNAL CPU
// DLD: DELAY LINE DRIVE
// FF1, 2: MEMORY LATCH

// THIS PLD WILL ARBITRATE THE LOCAL BUS FOR EXTERNAL ACCESS.
// REQUESTS HOLD FROM 188, THEN ALLOW EXTERNAL BUS ACCESS
// WHEN HLDA IS RETURNED. TO PREVENT PROBLEMS WITH
// BACK-TO-BACK CYCLES. A SECOND ACCESS WILL NOT BE
// PERMITTED UNTIL THE HOLD ACKNOWLEDGE FROM THE FIRST ACCESS
// HAS BEEN REMOVED BY THE LOCAL 188.
XWAIT = XSEL Be IFF2

HOLD = XWAIT & XRD & !HLDA
# XWAIT & XWR & !HLDA
#HOLD&XRD
#HOLD&XWR

// AFTER HOLD AND HLDA BOTH TRUE, TIMING CYCLE STARTS.
// EXTERNAL ADDRESS IS ENABLED FIRST. AFTER 40 NS SETW,
// LOCAL FtEAD/WRTTE IS ASSERTED. 100 NS AFTER THAT,
// XWAIT IS REMOVED TO COMPLETE CYCLE.
DLD = HOLD & HLDA & XRD & !FFl
#HOLD Be HLDA Be XWR & IFF1
FF1 = DL140
# FF1 & IFF2

214 Embedded Micropocessm Systems