Page 235 - Embedded Microprocessor Systems Real World Design

If the messages have variable length, the semaphore may be replaced with a
length byte (or word). CPU 1 places data in the buffer, then places the length at
the first byte. CPU 2 clears the length to zero when it has processed the data. This
makes more efficient use of the RAM since the buffer length is only as long as
needed for a particular message, and subsequent messages can be strung together
in memory, the length byte of one message immediately following the last byte of
the previous message. However, it makes the code less efficient because the CPU
must search through the buffers using the lengths to find the first unused one.
The length/semaphore must be set by the sending CPU only after the complete
message is in the buffer, or the receiving CPU may see the length byte and try to
read the message before it is completely written.
I have already mentioned data corruption in synchronous DPRAMs. Any type of
DPRAM arrangement is susceptible to data corruption if the memory is managed
poorly. In general, data buffers should be segregated into send and receive buffers.
One CPU writes to the send buffers while the other CPU reads them, and the
reverse is true for the other set of buffers. This arrangement is needed because, if
the buffers are shared, both processors may try to simultaneously grab an empty
buffer. If it is impossible to segregate the buffers this way, a protocol must be put
in place to keep both processors from attempting to access the same buffers at the
same time.
An additional problem can occur when using 8-bit DPRAM with 16-bit proces-
sors. If the semaphores and buffers are lfbbit words, the processors will have to do
two &bit memory cycles to access a lfbbit semaphore. It is possible for one proces-
sor to access a memory location in the middle of the two write cycles from the other
processor.
This problem can be avoided if the processors have a LOCK function, which can
be used to lock out access to the DPRAM by the other processor. However, this will
not work with a synchronous DPRAM design. In general, it is safest to have critical
semaphores be 8 bits wide in these applications. Use 8-bit semaphores to control
access to buffers, and, if necessary, use lfbbit counters and data values.

Serial Communication
Chapter 4 describes a method of communicating between a pair of ADSP-2101
processors using the built-in synchronous serial port. In that example, the serial
interface sent 16 bits at a time. The low-order byte (DO-D7) was designated as data,
D8 and D9 indicated the source of the transmission (up to four DSPs were possi-
ble in the system), D10 and D11 indicated the destination, and D12-Dl5 were an
opcode that indicated what the data were for. While this scheme required 16 bits
to be transmitted per byte, most opcodes require only 1 byte, and the mechanism
allows multiple devices to share the bus.

216 Embedded MacrOprocessor System