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number of nanoseconds before the latch goes low. If this requirement is not met, the output
will be indeterminate.
Figure C.3 shows the timing characteristics of the two types of latches. Registers and
latches commonly are packaged in 8- or 16-bit versions to match microprocessor data buses.
When packaged this way, all the latches or registers in the package are clocked to a common
clock or latch pin.
Latches and registers also are available with tristate outputs, where a common output
enable pin enables all the outputs in the package. There are even devices that combine a
transceiver and latch into a single package, making a bidirectional, latched (or registered)
transceiver.
Appendix C 323
