Page 51 - Embedded Microprocessor Systems Real World Design

Not all microprocessors support wait states; for example, most single-chip proces-
sors (such as 8051, PIC17C4x) do not have a provision for wait states. However,
most processors designed for multichip applications support wait states.

Internal Wait States
Some processors have internal logic that can insert wait states. These wait states
are programmed in software to extend processor cycles when accessing specific
memory or 1/0 addresses. The 80186 has several outputs that can be programmed
to generate chip selects at specific address ranges. These can be used to select
EPROM, RAM, or 1/0 devices. For each output, an internal wait state generator
can be programmed to automatically insert up to three wait states. They can also
be programmed to either accept or ignore wait requests from the external wait
signals.

Wait State Timing

When the processor starts a bus cycle and detects that the wait line is active, it will
extend the cycle, leaving the -RD, -WR, or -DS signal active and sampling the wait
line once per clock. Once the wait signal has gone inactive, indicating that the
peripheral is ready, the processor will complete the bus cycle. The wait input is con-
ceptually straightforward, but the details can cause problems. The most common
problem is timing assertion of the wait state, which requires study of the data sheets.
Figure 2.4 shows a (simplified) diagram of the 80186/80188 processor timing. The
SRDY (Synchronous ReaDY) input of the 80186 must be asserted before the second
falling clock edge after the ALE goes inactive. However, SRDY must be externally
synchronized by the user, so the peripheral actually must assert the wait request
right after the -RD or -WR signal. If the wait logic is delayed too much, the request
will occur too late and the processor will ignore it. Other processors have different
quirks that must be taken into account.
Some peripheral ICs include integral wait-state generators. If you use one of
these, be sure that the timing will work with the processor. Some peripheral ICs
assert the wait request too late in the cycle for some processors to recognize it.

Bus Types and Their Relationship to Wait States

Processors like the Intel x86 family use a normally-ready bus. They do not use a
bus-acknowledge signal and they default to no wait states. In other words, the input
(usually READY) that causes wait states to be inserted in the cycle normally is pulled
to the ready (no wait state) condition. If the external logic does not drive the input
to generate wait states, the processor generates the access cycle and continues on,
regardless of whether the peripheral was really ready.

36 Embedded Microprocessor Systems